Cryptography and error correction codes are widely used for information security and data integrity services in modern digital computing and communications systems. A number of standardized and published cryptography, and error correction algorithms utilize arithmetic operations over GF(2m) . The polynomial basis (PB) representation of GF(2m) elements is suitable for the support of multiple GF(2m) fields (that is, versatility). This article considers the problem of reduced hardware efficiency of versatile GF(2m) PB multipliers as a result of increased loading latency of the inputs and irreducible polynomial. In this context, to the best of our knowledge, this article proposes the first input-latency free versatile bit-serial GF(2m) multiplier using PB. The superiority of the proposed versatile PB multiplier is demonstrated for the case where the multiplication’s inputs arrive serially in terms of higher output throughput and hardware efficiency compared to existing versatile PB and Gaussian normal basis (GNB) counterparts based on the application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) realizations, respectively. The proposed versatile PB multiplier improves hardware efficiency by factors of 1.8 and 2.5, respectively, compared to the versatile PB and versatile GNB counterparts.
Software Implementation:
Modelsim
Xilinx
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