Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Original price was: ₹20,000.00.₹10,000.00Current price is: ₹10,000.00.
Source : Tanner EDA
Abstract:
In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.
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Proposed Title :
A 45nm CMOS Technology Exploring low power and Fast 4 bit Full Adder using XOR/XNOR Gates
Improvement of this Project:
In this project we proposed 1 bit full adder using 45nm CMOS technology and compare with Existing 65nm CMOS technology.
Software implementation:
- TANNER EDA
Proposed Abstract :
This paper, explores 4 bit full adder using XOR/XNOR or simultaneous XOR-XNOR gates and also consuming power and area of the circuit and increasing speed. This paper propose 4 bit full adder using full swing XOR/XNOR gates. The existing system simulated in 65nm CMOS technology and using hybrid 1 bit full adder. So it consumes more power for implementation. The proposed circuits simulation results based on 45nm CMOS technology model, it have superior speed and reducing area, power consumption and this circuit has high speed, low power using power delay product (PDP). In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with less iteration. In the proposed circuits new transistor sizing is implemented to optimize the PDP circuits. The proposed architecture results are compared with area, power and speed of the existing architecture.
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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
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