A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques
A 35-Gb/s PAM-4 Transmitter With 7B4Q
Full-Transition Avoidance and Area-Efficient
Gm-Boosting Techniques
Abstract:
This brief describes a channel-loss-tolerant 35-Gb/s PAM-4 transmitter with feed-forward equalization (FFE) for high-speed wireline interfaces. The proposed transmitter adopts 7B4Q full transition avoidance (FTA) coding in combination with the 2-tap FFE to improve the worst-case horizontal eye-opening in the presence of inter-symbol interference (ISI). The input and output bit widths (7-bit input and 8-bit (4Q) output) and the encoder structure are selected to achieve a high data-rate with a synthesizable encoder hardware. Additionally, an area-efficient gm-boosting voltage-mode driver is used to enhance the transition slope. The transmitter test chip was fabricated in a 28-nm CMOS process and occupied 0.18 mm2. The design achieved 35-Gb/s with a 0.95x wider horizontal eye-opening by adopting the FTA coding for a 5.2-dB loss channel.
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A 35-Gb/s PAM-4 Transmitter With 7B4Q
Full-Transition Avoidance and Area-Efficient
Gm-Boosting Techniques
