The evolution of microelectronics boosts more scalable and complex circuit designs, providing high processing speed and greater storage capacity. However, reliability issues have grown significantly as electronic devices scale down, increasing the fault rate, mainly in critical applications exposed to radiation. Memories are sensitive to charged particles, which can corrupt data due to the transient effects. Error correction codes (ECCs) are highly applied to mitigate data failures, increasing memory reliability. The matrix region selection code (MRSC) is an ECC designed to correct a high rate of adjacent errors in memory but less effectively for nonadjacent errors. However, MRSC has a 2-D structure that makes it challenging to implement in memory where one address is accessed at a time. This article introduces the triple burst error correction based on region selection code (TBEC-RSC), an ECC that uses MRSC concepts, converting the MRSC format to a 1-D structure. TBEC-RSC was implemented and evaluated in a 16-bit data version; however, the code is easily extensible to the higher base-2 data words (e.g., 64 bits). Experimental results showed that TBEC-RSC corrects 100% of triple burst errors and more than 40% of 8-bit burst errors.
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A Triple Burst Error Correction Based on Region Selection Code
