sale OFFER 36%

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

sale OFFER 40%

Area Efficient, VLSI, VLSI 2023

Design and Evaluation of Inexact Computation based Systolic Array for Convolution

sale OFFER 25%

2020, High speed VLSI Design, VLSI

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

sale OFFER 29%

Area Efficient, VLSI, VLSI 2024

Design and Implementation of 32-bit CSPRNG using the PRESENT cipher with Dual Polynomial PRNG for Enhanced Randomness and Precision

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient Deep Neural Networks

sale OFFER 33%

Low power VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

Design and Implementation of Arithmetic Logic Unit in DSCH3 and Microwind

sale OFFER 50%

VLSI, VLSI Application / Interface and Mini Projects

Design and Implementation of Arithmetic Logic Unit in HDL

sale OFFER 36%

2018, Image Processing, VLSI

Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder

sale OFFER 29%

2015, Area Efficient, IEEE, VLSI

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

sale OFFER 30%

2016, Low power VLSI Design

Design Methodology for Voltage Scaled Clock Distribution Networks

sale OFFER 40%

2015, Low power VLSI Design

Design of 4-bit Ripple carry adder and using 9T full adder

sale OFFER 40%

2020, Low power VLSI Design, VLSI

Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation

sale OFFER 50%

VLSI, VLSI Application / Interface and Mini Projects

Design of Approximate Restoring Divider

sale OFFER 40%

2018, Low power VLSI Design, VLSI

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder

sale OFFER 33%

2016, Low power VLSI Design, VLSI

Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

sale OFFER 44%

2017, Image Processing

Design of Power and Area Efficient Approximate Multipliers

sale OFFER 20%

2019, High speed VLSI Design, VLSI

Design of Reconfigurable Digital IF Filter with Low Complexity

sale OFFER 36%

2021, High speed VLSI Design, VLSI

Design of SEU Tolerant 2D-FFT in SRAM-based FPGA

sale OFFER 38%

2019, High speed VLSI Design, VLSI

Design of Sparse FIR Filters With Reduced Effective Length

sale OFFER 40%

2015, Area Efficient, IEEE, VLSI

Design of Testable Reversible Sequential Circuits

sale OFFER 30%

2021, Image Processing, VLSI

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

sale OFFER 36%

2020, Area Efficient, VLSI

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits

sale OFFER 30%

2017, Image Processing

Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers

sale OFFER 20%

2015, Low power VLSI Design

Dual Use of Power Lines for Design for Testability A CMOS Receiver Design

sale OFFER 44%

Area Efficient, VLSI, VLSI 2024

Efficient Approximate Floating-Point Multiplier with Runtime Reconfigurable Frequency and Precision

sale OFFER 28%

Area Efficient, VLSI, VLSI 2024

Efficient CRC-BCH Unified Encoder for Global Positioning System

sale OFFER 40%

2019, Area Efficient, VLSI

Efficient Design for Fixed-Width Adder-Tree

sale OFFER 50%

VLSI, VLSI Application / Interface and Mini Projects

Efficient Design of Behavioral Clock Divider for Multiple Frequency

sale OFFER 25%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

Efficient Image Conversion and Restoration System with Hexadecimal Encoding and Quality Evaluation

sale OFFER 50%

Area Efficient, VLSI, VLSI 2024

Efficient Pseudo Random Number Generator (PRNG) Design on FPGA

sale OFFER 29%

2017, Image Processing, VLSI

Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation

sale OFFER 44%

2018, Low power VLSI Design, VLSI

Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA

sale OFFER 40%

2017, Image Processing, VLSI

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

sale OFFER 44%

2017, Area Efficient, VLSI

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

sale OFFER 50%

2019, Low power VLSI Design, VLSI

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

sale OFFER 33%

ER_TCAM_A Soft Error Resilient SRAM Based TCAM

2020, Area Efficient, VLSI

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

sale OFFER 28%

Error_Detection_Correction_SRAM_Emulated_TCAM

2019, Area Efficient, VLSI

Error Detection and Correction in SRAM Emulated TCAMs

sale OFFER 33%

High speed VLSI Design, VLSI, VLSI 2023

Extraction of Fetal ECG from Abdominal and Thorax ECG Using a Non-Causal Adaptive Filter Architecture

sale OFFER 20%

High speed VLSI Design, VLSI, VLSI 2023

Fast and Hardware-Efficient Variable Step Size Adaptive Beamformer

sale OFFER 36%

2019, Area Efficient, VLSI

Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

sale OFFER 44%

2018, High speed VLSI Design, VLSI

FIR Filter Design based on FPGA

sale OFFER 38%

2016, High speed VLSI Design

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

sale OFFER 20%

2020, Image Processing, VLSI

Floating-point discrete wavelet transform-based image compression on FPGA

sale OFFER 54%

2021, High speed VLSI Design, VLSI

FPGA Based High Definition SPWM Generation With Harmonic Mitigation Property

sale OFFER 33%

2020, Area Efficient, VLSI

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

sale OFFER 43%

2019, High speed VLSI Design, VLSI

FPGA Heart Rate Monitoring (Pre Processing – QRS Detection Stage)

sale OFFER 33%

VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of 64 Block Data Encryption Standard Algorithm

sale OFFER 50%

VLSI Application / Interface and Mini Projects

FPGA Implementation of 8×8 Truncated Multiplier

sale OFFER 25%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of 8×8 Truncated Multiplier Using Brent Kung Parallel Prefix Adder

sale OFFER 50%

High speed VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of a ECG-DAC-SPI Interface for Medical Applications

sale OFFER 33%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Comparative Analysis and Performance Evaluation for Different LFSR Techniques

sale OFFER 60%

2021, High speed VLSI Design, VLSI

FPGA Implementation of D8PSK Demodulator

sale OFFER 28%

2021, High speed VLSI Design, VLSI

FPGA Implementation of Epileptic Seizure Detection Using ELM Classifier Detection Using ELM Classifier

sale OFFER 50%

VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of High Performance Reversible logic based 16×16 Array Multiplier

sale OFFER 33%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Image Line Buffer to Split and reconstruct a 3×3 size of image pixel with using FIFO Design

sale OFFER 44%

2020, Image Processing, VLSI

FPGA implementation of low power and high speed image edge detection algorithm

sale OFFER 33%

2015, Area Efficient, High speed VLSI Design

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

sale OFFER 20%

2022, Area Efficient, VLSI

FPGA Implementation of Single Precision Floating Point Multiplier using High Speed Parallel Prefix Adder based Wallace Tree Multiplier

sale OFFER 40%

High speed VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Spread Spectrum Clock Generator with Onion Modulation

sale OFFER 38%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of TFT 1.8 inch SPI 128×160 Display ROM Interface

sale OFFER 52%

2021, High speed VLSI Design, VLSI

FPGA Implementation of the Adaptive Digital Beamforming for Massive Array

sale OFFER 38%

2019, High speed VLSI Design, VLSI

FPGA-Based System For Heart Rate Monitoring

sale OFFER 25%

2016, IEEE, Low power VLSI Design, VLSI

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

sale OFFER 33%

2016, Low power VLSI Design

Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation

sale OFFER 28%

2015, Image Processing

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

sale OFFER 20%

2015, Area Efficient

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

sale OFFER 38%

2018, Low power VLSI Design, VLSI

Gate diffusion input based 4-bit Vedic multiplier design

sale OFFER 20%

2015, Low power VLSI Design

Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC

sale OFFER 50%

VLSI, VLSI Application / Interface and Mini Projects

Hamming based Single Fault Error Correction Code

sale OFFER 33%

2022, Image Processing, VLSI

Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm

sale OFFER 52%

Area Efficient, VLSI, VLSI 2024

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

sale OFFER 55%

Image Processing, VLSI, VLSI 2024

Hardware-Optimized High-Quality Super-Resolution Accelerator for Real-Time Edge Computing

sale OFFER 44%

2016, Low power VLSI Design, VLSI

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

sale OFFER 33%

2021, Area Efficient, VLSI

High Performance Accurate and Approximate Multipliers for FPGA based Hardware Accelerators

sale OFFER 33%

High speed VLSI Design, VLSI, VLSI 2023

High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing

sale OFFER 36%

2017, High speed VLSI Design

High Performance VLSI architecture for M-PSK modems

sale OFFER 38%

2015, Area Efficient

High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

sale OFFER 25%

2018, Area Efficient, VLSI

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

sale OFFER 52%

2020, Area Efficient, VLSI

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

sale OFFER 45%

2016, High speed VLSI Design

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

sale OFFER 33%

2020, Area Efficient, VLSI

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Highly Linear Low-Power Wireless RF Receiver for WSN

sale OFFER 36%

Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

Hybrid Protection of Digital FIR Filters

sale OFFER 43%

2022, Image Processing, VLSI

Image Demosaicking using Super Resolution Techniques

sale OFFER 57%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

Image Encryption on FPGA Using Chaotic PRNG and LFSR: TFT Display Integration

sale OFFER 40%

Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process

sale OFFER 18%

Area Efficient, VLSI, VLSI 2023

Implementation of High-Precision MFCC Feature Extraction Using FPGA for Speech Recognition

sale OFFER 40%

2020, Area Efficient, VLSI

Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology

sale OFFER 33%

2015, Low power VLSI Design

Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application

sale OFFER 30%

2018, Area Efficient

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

sale OFFER 50%

2016, IEEE, NOC VLSI Design, VLSI

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

sale OFFER 33%

2016, Area Efficient

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

sale OFFER 20%

2019, Low power VLSI Design, VLSI

Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter

sale OFFER 33%

High speed VLSI Design, VLSI, VLSI 2023

Invasive RLS-Based Fetal ECG Extraction with Optimized Shift-and-Add Multiplier for Area-Efficient FPGA Implementation

sale OFFER 40%

2015, Image Processing

JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video

sale OFFER 33%

2018, Low power VLSI Design, VLSI

LECTOR: A Technique for Leakage Reduction in CMOS Circuits

sale OFFER 20%

2015, Low power VLSI Design

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

sale OFFER 44%

2019, High speed VLSI Design, VLSI

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

sale OFFER 44%

2022, Area Efficient, VLSI

Low Cost Online Convolution Checksum Checker

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