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2014

IEEE Transactions on VLSI 2014

Showing all 12 results

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A Floating-Point Fused Dot-Product Unit
~~₹15,000.00~~ ₹10,000.00
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A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving
~~₹10,000.00~~ ₹7,000.00
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A Low Cost Low Power All Digital Spread Spectrum Clock Generator
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An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation
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An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
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Area Delay Power Efficient Carry Select Adder
~~₹10,000.00~~ ₹5,000.00
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Data Encoding Techniques for Reducing Energy Consumption in Network on Chip
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Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
~~₹15,000.00~~ ₹8,000.00
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Design and Implementation of Turbo Coder for LTE on FPGA
~~₹10,000.00~~ ₹4,000.00
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Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
~~₹10,000.00~~ ₹7,000.00
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Recursive Approach to the Design of a Parallel Self Timed Adder
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Sharing Logic for Built In Generation of Functional Broadside Tests
~~₹10,000.00~~ ₹4,000.00
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