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Low power VLSI Design

Showing 1–16 of 42 results

Sale!
40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
~~₹10,000.00~~ ₹7,000.00
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A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
~~₹15,000.00~~ ₹10,000.00
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Sale!
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage
~~₹12,000.00~~ ₹8,000.00
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Sale!
A 6-GS/s 6-bit Time Interleaved SAR-ADC
~~₹12,000.00~~ ₹8,000.00
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A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply
~~₹10,000.00~~ ₹9,000.00
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A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving
~~₹10,000.00~~ ₹7,000.00
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A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
~~₹12,000.00~~ ₹8,000.00
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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
~~₹10,000.00~~ ₹6,000.00
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Sale!
A Low Cost Low Power All Digital Spread Spectrum Clock Generator
~~₹15,000.00~~ ₹6,000.00
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Sale!
A Low Power Architecture for the Design of a One Dimensional Median Filter
~~₹10,000.00~~ ₹7,000.00
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Sale!
A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications
~~₹10,000.00~~ ₹6,000.00
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A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization
~~₹10,000.00~~ ₹6,000.00
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Sale!
A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit
~~₹10,000.00~~ ₹6,000.00
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Sale!
Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks
~~₹10,000.00~~ ₹7,000.00
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Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
~~₹10,000.00~~ ₹6,000.00
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Sale!
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
~~₹10,000.00~~ ₹5,000.00
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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

A 6-GS/s 6-bit Time Interleaved SAR-ADC

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

A Low Power Architecture for the Design of a One Dimensional Median Filter

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency