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Low power VLSI Design

Showing all 54 results

Sale!
40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
~~₹10,000.00~~ ₹7,000.00
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Sale!
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
~~₹15,000.00~~ ₹10,000.00
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Sale!
A 13.4-MHz Relaxation Oscillator With Temperature Compensation
~~₹10,000.00~~ ₹6,000.00
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Sale!
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage
~~₹12,000.00~~ ₹8,000.00
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Sale!
A 6-GS/s 6-bit Time Interleaved SAR-ADC
~~₹12,000.00~~ ₹8,000.00
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Sale!
A 7T Security Oriented SRAM Bitcell
~~₹12,000.00~~ ₹4,000.00
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Sale!
A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply
~~₹10,000.00~~ ₹9,000.00
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Sale!
A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving
~~₹10,000.00~~ ₹7,000.00
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Sale!
A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
~~₹12,000.00~~ ₹8,000.00
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Sale!
A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity
~~₹16,000.00~~ ₹10,000.00
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Sale!
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
~~₹10,000.00~~ ₹6,000.00
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Sale!
A Low Cost Low Power All Digital Spread Spectrum Clock Generator
~~₹15,000.00~~ ₹10,000.00
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Sale!
A Low Power Architecture for the Design of a One Dimensional Median Filter
~~₹10,000.00~~ ₹7,000.00
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Sale!
A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications
~~₹10,000.00~~ ₹6,000.00
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Sale!
A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization
~~₹10,000.00~~ ₹6,000.00
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Sale!
A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift
~~₹12,000.00~~ ₹6,000.00
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Sale!
A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit
~~₹10,000.00~~ ₹6,000.00
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Sale!
Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks
~~₹10,000.00~~ ₹7,000.00
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Sale!
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
~~₹10,000.00~~ ₹6,000.00
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Sale!
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
~~₹10,000.00~~ ₹6,000.00
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Sale!
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
~~₹10,000.00~~ ₹5,000.00
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Sale!
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
~~₹12,000.00~~ ₹6,000.00
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Sale!
Design Methodology for Voltage Scaled Clock Distribution Networks
~~₹10,000.00~~ ₹7,000.00
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Sale!
Design of 4-bit Ripple carry adder and using 9T full adder
~~₹8,000.00~~ ₹3,000.00
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Sale!
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
~~₹10,000.00~~ ₹4,000.00
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Sale!
Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
~~₹15,000.00~~ ₹6,000.00
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Sale!
Dual Use of Power Lines for Design for Testability A CMOS Receiver Design
~~₹10,000.00~~ ₹4,000.00
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Sale!
Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA
~~₹15,000.00~~ ₹10,000.00
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Sale!
Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
~~₹12,000.00~~ ₹6,000.00
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Sale!
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
~~₹10,000.00~~ ₹7,500.00
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Sale!
Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation
~~₹10,000.00~~ ₹6,000.00
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Sale!
Gate diffusion input based 4-bit Vedic multiplier design
~~₹16,000.00~~ ₹10,000.00
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Sale!
Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
~~₹15,000.00~~ ₹10,000.00
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Sale!
HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic
~~₹12,000.00~~ ₹6,000.00
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Sale!
Highly Linear Low-Power Wireless RF Receiver for WSN
~~₹12,000.00~~ ₹8,000.00
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Sale!
Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application
~~₹8,000.00~~ ₹4,000.00
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Sale!
Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter
~~₹10,000.00~~ ₹7,000.00
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Sale!
LECTOR: A Technique for Leakage Reduction in CMOS Circuits
~~₹12,000.00~~ ₹6,000.00
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Sale!
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
~~₹8,000.00~~ ₹3,000.00
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Sale!
Low Power and Area Efficient Shift Register Using Pulsed Latches
~~₹10,000.00~~ ₹6,000.00
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Sale!
Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier
~~₹16,000.00~~ ₹10,000.00
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Sale!
Low Power ECG Based Processor for Predicting Ventricular Arrhythmia
~~₹50,000.00~~ ₹20,000.00
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Sale!
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
~~₹10,000.00~~ ₹7,500.00
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Sale!
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
~~₹12,000.00~~ ₹6,000.00
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Sale!
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
~~₹15,000.00~~ ₹10,000.00
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Sale!
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications
~~₹10,000.00~~ ₹5,000.00
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Sale!
Multiloop Control for Fast Transient DC–DC Converter
~~₹18,000.00~~ ₹12,000.00
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Sale!
Quaternary Logic Lookup Table in Standard CMOS
~~₹8,000.00~~ ₹4,000.00
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Sale!
Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application
~~₹12,000.00~~ ₹8,000.00
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Sale!
Recursive Approach to the Design of a Parallel Self Timed Adder
~~₹10,000.00~~ ₹6,000.00
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Sale!
Resource Efficient SRAM based Ternary Content Addressable Memory
~~₹16,000.00~~ ₹10,000.00
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Sale!
Source Code Error Detection in High Level Synthesis Functional Verification
~~₹15,000.00~~ ₹10,000.00
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Sale!
To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹4,500.00
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Sale!
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
~~₹15,000.00~~ ₹10,000.00
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Cart

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

A 6-GS/s 6-bit Time Interleaved SAR-ADC

A 7T Security Oriented SRAM Bitcell

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

A Low Power Architecture for the Design of a One Dimensional Median Filter

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

Design Methodology for Voltage Scaled Clock Distribution Networks

Design of 4-bit Ripple carry adder and using 9T full adder

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

Dual Use of Power Lines for Design for Testability A CMOS Receiver Design

Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation

Gate diffusion input based 4-bit Vedic multiplier design

Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

Highly Linear Low-Power Wireless RF Receiver for WSN

Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application

Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter

LECTOR: A Technique for Leakage Reduction in CMOS Circuits

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

Low Power and Area Efficient Shift Register Using Pulsed Latches

Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier

Low Power ECG Based Processor for Predicting Ventricular Arrhythmia

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

Multiloop Control for Fast Transient DC–DC Converter

Quaternary Logic Lookup Table in Standard CMOS

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

Recursive Approach to the Design of a Parallel Self Timed Adder

Resource Efficient SRAM based Ternary Content Addressable Memory

Source Code Error Detection in High Level Synthesis Functional Verification

To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier