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vlsi ieee projects in pondicherry
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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
$
150.00
$
105.00
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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
$
105.00
$
90.00
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Sale!
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
$
150.00
$
90.00
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A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
$
150.00
$
105.00
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Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems
$
150.00
$
90.00
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Design of Testable Reversible Sequential Circuits
$
150.00
$
60.00
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Sale!
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
$
150.00
$
112.50
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Sale!
Graph-Based Transistor Network Generation Method for Supergate Design
$
150.00
$
60.00
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Sale!
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
$
150.00
$
90.00
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Sale!
Low Power and Area Efficient Shift Register Using Pulsed Latches
$
150.00
$
90.00
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Sale!
Low Power Divider Using Vedic Mathematics
$
150.00
$
105.00
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Sale!
Low Power Variation Tolerant Nonvolatile Lookup Table Design
$
150.00
$
112.50
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Sale!
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
$
150.00
$
112.50
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Sale!
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
$
150.00
$
90.00
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Sale!
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
$
150.00
$
120.00
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Sale!
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
$
150.00
$
90.00
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To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics
$
150.00
$
67.50
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