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vlsi ieee projects

Showing 1–16 of 50 results

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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
~~₹10,000.00~~ ₹7,000.00
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A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform
~~₹25,000.00~~ ₹20,000.00
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A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply
~~₹10,000.00~~ ₹9,000.00
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A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving
~~₹10,000.00~~ ₹7,000.00
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A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
~~₹12,000.00~~ ₹8,000.00
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A High Speed FPGA Implementation of an RSD Based ECC Processor
~~₹15,000.00~~ ₹10,000.00
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A Low Cost Low Power All Digital Spread Spectrum Clock Generator
~~₹15,000.00~~ ₹6,000.00
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A Low Power Architecture for the Design of a One Dimensional Median Filter
~~₹10,000.00~~ ₹7,000.00
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A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network
~~₹35,000.00~~ ₹25,000.00
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A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography
~~₹7,000.00~~ ₹6,000.00
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A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM
~~₹15,000.00~~ ₹8,000.00
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A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit
~~₹10,000.00~~ ₹6,000.00
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A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction
~~₹10,000.00~~ ₹7,000.00
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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
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Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks
~~₹10,000.00~~ ₹7,000.00
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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
~~₹10,000.00~~ ₹7,000.00
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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A High Speed FPGA Implementation of an RSD Based ECC Processor

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

A Low Power Architecture for the Design of a One Dimensional Median Filter

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.