+91 9789443203

vlsi ieee projects

Showing all 49 results

Sale!
A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform
~~₹25,000.00~~ ₹20,000.00
Add to cart
Sale!
A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply
~~₹10,000.00~~ ₹9,000.00
Add to cart
Sale!
A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
~~₹12,000.00~~ ₹8,000.00
Add to cart
Sale!
A High Speed FPGA Implementation of an RSD Based ECC Processor
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
A Low Cost Low Power All Digital Spread Spectrum Clock Generator
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
A Low Power Architecture for the Design of a One Dimensional Median Filter
~~₹10,000.00~~ ₹8,000.00
Add to cart
Sale!
A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network
~~₹35,000.00~~ ₹25,000.00
Add to cart
Sale!
A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography
~~₹7,000.00~~ ₹6,000.00
Add to cart
Sale!
A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM
~~₹15,000.00~~ ₹8,000.00
Add to cart
Sale!
A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation
~~₹15,000.00~~ ₹8,000.00
Add to cart
Sale!
Area Delay Power Efficient Carry Select Adder
~~₹10,000.00~~ ₹5,000.00
Add to cart
Sale!
ASIC design of UHF RFID reader digital baseband
~~₹12,000.00~~ ₹6,000.00
Add to cart
Sale!
Block Interleaver Design for High Data Rate Wireless Networks
~~₹20,000.00~~ ₹12,000.00
Add to cart
Sale!
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Data Encoding Techniques for Reducing Energy Consumption in Network on Chip
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Design and Analysis of Approximate Compressors for Multiplication
~~₹15,000.00~~ ₹7,000.00
Add to cart
Sale!
Design of 4-bit Ripple carry adder and using 9T full adder
~~₹8,000.00~~ ₹3,000.00
Add to cart
Sale!
Design of Testable Reversible Sequential Circuits
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
Dual Use of Power Lines for Design for Testability A CMOS Receiver Design
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
Add to cart
Sale!
Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator
~~₹12,000.00~~ ₹8,000.00
Add to cart
Sale!
Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application
~~₹8,000.00~~ ₹4,000.00
Add to cart
Sale!
JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
~~₹8,000.00~~ ₹3,000.00
Add to cart
Sale!
Low Power Compressor Based MAC Architecture for DSP Applications
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Low Power ECG Based Processor for Predicting Ventricular Arrhythmia
~~₹50,000.00~~ ₹20,000.00
Add to cart
Sale!
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
~~₹12,000.00~~ ₹9,000.00
Add to cart
Sale!
Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Obfuscating DSP Circuits via High Level Transformations
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Quaternary Logic Lookup Table in Standard CMOS
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Quaternary Logic Lookup Table in Standard CMOS
~~₹8,000.00~~ ₹4,000.00
Add to cart
Sale!
Recursive Approach to the Design of a Parallel Self Timed Adder
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array
~~₹20,000.00~~ ₹12,000.00
Add to cart
Sale!
Sharing Logic for Built In Generation of Functional Broadside Tests
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
VHDL Implementation of Public key Cryptography based Image encryption and decryption using Reversible data LSB algorithm
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
VLSI Implementation of Efficient Image Watermarking Algorithm
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet
~~₹15,000.00~~ ₹6,000.00
Add to cart

Cart

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A High Speed FPGA Implementation of an RSD Based ECC Processor

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

A Low Power Architecture for the Design of a One Dimensional Median Filter

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

Area Delay Power Efficient Carry Select Adder

ASIC design of UHF RFID reader digital baseband

Block Interleaver Design for High Data Rate Wireless Networks

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

Data Encoding Techniques for Reducing Energy Consumption in Network on Chip

Design and Analysis of Approximate Compressors for Multiplication

Design of 4-bit Ripple carry adder and using 9T full adder

Design of Testable Reversible Sequential Circuits

Dual Use of Power Lines for Design for Testability A CMOS Receiver Design

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application

JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

Low Power Compressor Based MAC Architecture for DSP Applications

Low Power ECG Based Processor for Predicting Ventricular Arrhythmia

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

Obfuscating DSP Circuits via High Level Transformations

Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

Quaternary Logic Lookup Table in Standard CMOS

Quaternary Logic Lookup Table in Standard CMOS

Recursive Approach to the Design of a Parallel Self Timed Adder

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

Sharing Logic for Built In Generation of Functional Broadside Tests

VHDL Implementation of Public key Cryptography based Image encryption and decryption using Reversible data LSB algorithm

VLSI Implementation of Efficient Image Watermarking Algorithm

VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet