Proposed Title :

A 0.25V SNDR Asynchronous Delta-Sigma Modulator with 8-Bit DAC in 45nm CMOS

Improvement of this Project:

• • To design a SNDR Asynchronous Delta–Sigma Modulator in 45nm CMOS Technology with 25V and proved the comparison with existing 0.18um SNDR Asynchronous Delta–Sigma Modulator.

  • To design a SNDR Asynchronous Delta–Sigma Modulator with 1-Bit DAC to SNDR Asynchronous Delta–Sigma Modulator with 8-Bit DAC with 0.2V and get the terms of Area and Power.

Software implementation:

• Tanner EDA

Proposed System:

In recent years, ULV – (ultra low voltage) BD (bulk driven) circuits are significant in wireless applications powered form non-conventional energy sources. ADC and DAC are surviving an important role in analog and digital circuits. A Delta-Sigma Modulator (DSM) method used for encoding in data convertor technique. In existing, with 1-bit DAC, a fully differential ADSM designed. In this proposed system, which proven the minimum supply voltage of 0.25V for ADSN (Asynchronous Delta Sigma Modulator) is designed with eight-bit cell DAC. A proposed ADSM designed with DAC 8 bit cell, with the help of Gm-C integrator and hysteretic comparator. Finally, the proposed circuit is implemented in the TANNER EDA at 45nm CMOS Technology with 0.25V input voltage and proved the comparison in terms of area and power.

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