Proposed Title :

FPGA Implementation of  High Speed 64-bit Data Width True Random Number Generator Using Clock Managers and Metastability

Improvement of this project :

• To design the TRNG Core for 64-bit data width, and compared that to 32-bit TRNG Core data width.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

True random number generators, often known as TRNGs, are essential components of a wide variety of critical security applications. Despite the fact that digital-based solutions take use of randomness sources that are often found in the analogue domain, digital-based solutions are highly needed, particularly when they need to be implemented on Field Programmable Gate Array (FPGA)-based digital systems. In this research, an unique technique that makes the design of a TRNG on FPGA devices more straightforward is described. In order to adjust the phase shift between two clock signals, it takes use of the runtime capabilities of the hardware primitives provided by the Digital Clock Manager (DCM). The auto-tuning approach that is being given automatically adjusts the phase difference between two clock signals in order to compel one or more flip-flops (FFs) to enter the metastability zone. This region is used as a source of unpredictability in the system. In addition, an unique use of the fast carry-chain hardware primitive is offered as a means of further increasing the level of randomness present in the bits that are created. In final, a powerful on-chip post-processing strategy that does not inhibit the TRNG throughput is outlined here. This work was built in 32 and 64 data width, in verilog HDL, and synthesized in Xilinx Zynq FPGA. All of the characteristics were evaluated with regard to area, latency, and power consumption.

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A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers