Proposed Title :

• A 16-nm High Speed and Highly Efficient Conditional Flip Flops for High Speed Application using CMOS Technology

  (TGFF, MHLFF, SCDFF, CEPFF, SFTPFF, CDMPFF, (Pulse Triggered FFs) P-FFs)

Improvement of this Project:

• To reduce the number of possible transistor in Feed through pulsed flip flop of TGFF, MHLFF, SCDFF, CEPFF, SFTPFF, CDMPFF, Proposed (Pulse Triggered FFs ) P-FFs.

• Design this all pulsed Flip Flops at 16 nm CMOS Technology and proved the performance of delay reduction in Proposed P-FFs.

Software implementation:

• TANNER EDA

Proposed Abstract:

In recent digital applications will required highly efficient and high speed gadgets, its related to minimum delay and power consumptions. Thus, this proposed work of this paper will present a novel type of conditional feed through pulse triggered flip-flop. The data output of this flip flop was highly optimized using pre-discharging and conditional signal feed through schemes and the power consumption also reduced using shared pulse generator and an output feedback conditional keeper, which diminished the floating status of the internal node. This proposed work will compared this pulse triggered flip flop to seven different conventional topology flip flops at 16-nm CMOS Technology in such as Transmission gate flip flop (TGFF), Modified Hybrid latch flip flop (MHLFF), static latch conditional-discharge flip-flop (SCDFF), conditional pulse enhancement pulse triggered flip flop (CEPFF), signal feed through pulse triggered flip flop (SFTPFF), conditional data mapping pulse triggered flip flop (CDMPFF). Hence, the proposed work to reduce the number of transistor in Feed through pulsed triggered flip flop  and proved the performance of delay reduction in Proposed P-FFs.

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A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

(TGFF, MHLFF, SCDFF, CEPFF, SFTPFF, CDMPFF, (Pulse Triggered FFs) P-FFs)

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