Existing Design:
A median filter is a nonlinear filter widely used in digital signal and image processing for the smoothing of signals, suppression of impulse noise, and edge preservation. The median filter replaces a sample with the middle-ranked value among all the samples inside the sample window, centred on the sample in question. Depending on the number of samples processed at the same cycle, there are two types of architectures for hardware design, i.e., word-level architecture and bit-level architecture. In the word-level architecture, the input samples are sequentially processed word by word, and the bits of the sample are processed in parallel. On the contrary, the bit-level architecture processes the samples in parallel and the bits of the incoming samples are sequentially
Processed: In this brief, the word-level architecture will be adopted in the design of a low-power median filter for practical use.
The median of a set of samples in the word-level sorting network is often computed by first sorting the input samples and then selecting the middle value. In their methods, the input samples are sequentially processed word by word, and the incoming sample is inserted into the correct rank in two steps. In the first step, the oldest sample is removed from the window by moving some of the stored samples to the left. In the second step, the incoming sample is compared with the already sorted samples and then inserted in the right place by moving some of them to the right. The difference between the two architectures that these two steps are separately performed in two clock cycles, whereas it takes only one cycle. In both of their methods, however, some of the stored samples have to be shifted left or right, depending on their values when a new input sample enters the window. For some applications that require a larger sample width, more signal transitions in the circuit are needed; i.e., more dynamic power will be consumed. To conquer this problem, a new median filter architecture targeting low power consumption is proposed. Instead of sorting the samples physically in the window, the stored samples are kept immobile there. Only the rank of each sample, which uses fewer bits, has to be updated at each new cycle when an input sample enters the window. Since our architecture is implemented as a two-stage pipeline, the median output, which is the sample with median rank, will also be generated at each cycle. The improvement in power consumption is achieved by utilizing a token ring in our architecture. Since the stored samples in the window are immobile, our architecture is suitable for low-power applications.
Disadvantages:
- More area
- More power dissipation
Proposed Design:
The proposed design will be designed for the same architecture of existing work, and we are increasing the number of bit size level, in existing work it will be design for 5 bit architecture, and the proposed design will be designed for 8-bit architecture, and reduce the power dissipation compared to the existing work.
Advantages:
- Same area will be maintained at the existing work
- Increases the power consumption
Software used:
- Modelsim for simulation
- Xilinx for synthesis and routing
