Proposed Title :
FPGA Implementation of 128-Bit Advance Encryption and 128-Bit Advance Decryption design using 32-bit Memory Block with Automated key generation
Improvement of this project :
To design a Advance Encryption Standard and Advance Decryption Standard at 128 Data Width automated key generation with 32-bit Burst based Memory Block and proved the comparisons in Zynq 7000 FPGA using Xilinx VIVADO.
- Xilinx – Vivado
In a recent information security based application will be challenging also growing constantly due to technology improvement. The hackers take advantages of the latest sophisticated equipment and technology also breaking down on every safety device. Therefore, recent information security is increasingly dependent on information protection, either software or hardware implementation to ensure data privacy. This proposed work uses a hardware implementation of field programmable gate array unit, which has less complexity, more flexible and provides more energy efficiency. The emphasis of this work is on the hardware implementation of the Advance Encryption Standard (AES) as a cryptographic algorithm. The proposed algorithm will have developed a comparative analysis of 128-Bit data width using 32-bit memory block with automated key generation, and also implemented with encryption and decryption standard. This proposed algorithm will have developed in Zynq 7000 FPGA using Xilinx Vivado and compared all the parameters.
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Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation
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