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Camouflaged Logic Gates Using Threshold-Voltage-Defined Memory Cells
Original price was: ₹10,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : Tanner EDA
Base paper abstract:
This brief proposes two types of camouflaged logic gates using threshold-voltage-defined memory cells (TVD-MCs). The proposed multiplexer-select TVD-MC (MS-TVDMC) gate consists of a target logic gate, several camouflage logic gates, a multiplexer (MUX), and TVD-MCs. All logic gates and MUX are implemented with standard threshold-voltage transistors. The TVD-MC is composed of two cross coupled inverters with low- or high-threshold-voltage transistors. When its supply voltage increases from ground to VDD, its data become “0” or “1” according to the threshold voltages of transistors in two inverters. The target logic gate is selected with the MUX by the data stored in the TVD-MCs. The data are defined by the threshold voltages of transistors, so that it is difficult to distinguish the target logic gate from the other camouflage logic gates. The proposed logic-merged TVD-MC (LM-TVDMC) gate merges all logic gates and MUX in the MS-TVDMC gate at the transistor level. The proposed camouflaged gates significantly reduce the delay, power consumption, and leakage current compared to the conventional dynamic enhanced-TVD (DE-TVD) camouflaged gate requiring the dynamic power and delay overheads and the conventional threshold-voltage-defined (TVD) switch camouflaged gate with large ON-resistances in switch transistors. Index Terms: Camouflaged gate, logic gate, reverse engineering, security, threshold-voltage-defined (TVD).
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1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Camouflaged logic circuits are widely used in secure VLSI applications such as defence electronics, cryptographic processors, and intellectual property protection, where resistance to reverse engineering is critical. Threshold-voltage-based camouflaging techniques offer strong security without altering layout patterns, providing advantages such as invisibility to optical inspection and compatibility with standard CMOS processes; however, existing approaches often suffer from increased power consumption, large delay, complex dynamic circuitry, and area overhead. In current research, camouflaged gates based on dynamic threshold-voltage logic and threshold-defined switch designs have been demonstrated, but these methods introduce dynamic power overhead, leakage issues, or degraded performance due to weakly turned-on transistors. To address these limitations, this work proposes the development of a camouflage logic gate using a threshold-voltage-defined memory cell implemented in 45 nm CMOS technology, focusing on reducing power consumption, propagation delay, and silicon area while maintaining strong security against reverse engineering. The proposed design uses static CMOS logic combined with threshold-voltage-defined memory cells to select the intended logic function, eliminating dynamic pre charge operations and minimizing leakage current. In addition, the proposed camouflaged logic gate is extended to design key sequential circuits, including a data flip-flop and a shift register, demonstrating its suitability for practical digital system applications. The novelty of this work lies in integrating low-overhead camouflaged logic into both combinational and sequential circuits using a scalable 45 nm CMOS implementation. Performance evaluation is carried out through schematic design, layout implementation, and post-layout simulations using Tanner EDA tools, where parameters such as power consumption, delay, area, and leakage current are analysed and compared with conventional designs to validate the effectiveness of the proposed approach.
Software Implementation:
- Tanner EDA
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Design of Low Power Threshold Voltage Based Camouflaging Technique for Secure Combinational and Sequential VLSI Circuits
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