Proposed Title :
FPGA Implementation of Turbo Encoding and Decoding for LTE
Turbo codes, first proposed in 1993 , represent a breakthrough in channel coding techniques, since they have the potential to enable data transmission at rates close to the Shannon limit. They have been adopted for error control coding in the high speed downlink packet access (HSDPA) standard by the third-generation partnership project (3GPP), which considerably enhance the throughput for data-centric 3G modems.LTE specifies the use of turbo-codes to ensure reliable communication. Turbo codes were introduced in 1993 by Berrou, Glavieux and Thitimajashima , , reported extremely impressive results for a code with a long frame length. Since its recent invention, turbo coding has evolved at an unprecedented rate and has reached a state of maturity within just a few years due to the intensive research efforts of the turbo coding community. Simply put, a turbo code is formed from the parallel concatenation of two codes separated byan interleaver.
- Power consumption is high
The turbo encoder specified in the LTE standard is illustrated in Figure 1 and consists of a feed-through, two 4-state recursive convolutional encoders (CEs), and an interleaver. LTE employs a rate 1/3 parallel concatenated turbo code. The corresponding encoder is comprised of two rate 1/2 recursive systematic convolutional encoders.
The first component encoder receives un-coded (systematic) data bits xk in natural order and outputs a set of parity bits xk p1.The second CE receives an interleaved sequence xπ(k)of the information bits, where stands for the interleaved address associated with address, and generates a second sequence of parity bits.
Decoding of turbo codes is usually performed with the BCJR algorithm. The basic idea behind the turbo decoding algorithm is to iterate between two soft input soft-output (SISO) component decoders as illustrated in Figure 2. It consists of a pair of decoders which work cooperatively in order to refine and improve the estimate of the original information bits. The first and second SISO Decoder performs decoding of the convolutional code generated by the first or the second CE, respectively. A turbo-iteration corresponds to one pass of the first component decoder followed by a pass of the second component decoder. The operation performed by a single component decoder is referred to as a half-iteration
A soft-in-soft-out (SISO) decoder receives as input a “soft” (i.e. real) value of the signal. The decoder then outputs for each data bit an estimate expressing the probability that the transmitted data bit was equal to one.
The choice of the interleaver is a crucial part in the turbo code design. Interleavers scramble data in a pseudo-random order to minimize the correlation of neighboring bits at the input of the convolutional encoders.
- Reduced the power consumption
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