Proposed Title :
A 16nm CMOS Implementation of 64-Bit Fast Computation Hybrid Full Adder design for Scalable Application
Improvement of this Project:
To design the Fast computation 64-Bit Hybrid Full Adder at 22nm and 16nm CMOS technology and compared all the parameters in terms of area and power.
- Tanner EDA
This paper introduce a novel hybrid full adder architecture based on pass transistor (PTs), Transmission Gate (TGs), and conventional complementary metal oxide semiconductor (CCMOS) logic. For the comparative study, the efficiency of parameters have been compared with twenty number of existing hybrid full adder design, and finally get the proposed modified full adder using transmission gate and pass transistor method, it will reduce huge logic sizes and power consumptions. In order to verify its scalability, the proposed full adder has also been expanded up to a word length of 64 data bits. This proposed method of hybrid full adder architecture will more suitable for recent high speed central processing units. This work was designed in Tanner EDA tool at 22nm and 16nm CMOS Technology, this design outperforms in terms of power consumptions and latency in very low level.
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Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation
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