Proposed Title :

• Multiply–Accumulate Unit for the Machine Learning Accelerator using Feed forward-Cutset-Free Pipelined Technique.

Improvement of this Project:

• To Design a Column addition Pipeline architecture by using the concept of half adder, full adder and 4:2 compressor technique.

• To implement this Column addition stage in the MFCF_PA(Modified Feed forward free) technique in pipelined architecture.

• Finally, design the MAC(Multiply Accumulate Unit) by applying the MFCF_PA logic.

Software implementation:

• Modelsim
• Xilinx 14.2

Proposed System:

MAC(Multiply Accumulate Unit) computation plays a important role in (DSP) Digital Signal Processing.  The MAC is common step that computes the product of two numbers and add that product to an accumulator.  Generally, the Pipelined architecture is used to improve the performance by reducing the length of the critical path.  But, more number of flip flops are used when using the pipeline architecture that reduces the efficiency of MAC and increases the power consumption.  On the basis of machine learning algorithm, this paper proposes a feed forward-cutset-free (FCF) pipelined MAC architecture that is specialized for a high-performance machine learning accelerator, and also proposes the new design concept of MFCF_PA using the concept of column addition stage with the 4:2 compressor. Therefore, the proposed design method reduces the area and the power consumption by decreasing the number of inserted flip-flops for the pipelining when compared to the existing pipelined architecture for MAC computation.  Finally, the proposed feed forward cutset free pipelined architecture for MAC is implemented in the VHDL and synthesized in XILINX and compared in terms of area, power and delay reports.

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Feed Forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

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