Proposed Title :
FPGA Implementation of Harvard Architecture based True Random Number Generator to Prevent a Bottleneck in the Oscillator Rings
Improvement of this Project
To use Harvard method of bias corrector architecture in the output bit sequence instead of Von Neumann bias corrector.
- Xilinx 14.2
In cryptographic schemes real random number generators play an essential role. This paper introduces a new and powerful approach for generating truly random numbers on a programmable field gate array by using the random jitter of free running oscillators as a source of randomness. In order to produce broad variations of oscillations and to inject jitter into the generated ring oscillator clocks, the free running oscillator rings integrate programmable delay lines. The key benefits of the proposed true random number generator using programmable delay lines is to reduce the similarity between many oscillator rings of equal length and thereby increase the consistency of randomness. Furthermore, to eradicate any bias in the performance bit list, a Harvard architecture based corrector as a post processor is used to avoid bottleneck in oscillator rings. Validation of the suggested solution synthesized on Xilinx Spartan-6 FPGA with support of Verilog HDL, and the parameters in terms of area, delay and power were analyzed.
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FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
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