FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder

• To Design 8-Bit, 16-Bit and 32-Bit Proposed Three Operand Adder, with using Kogge Stone parallel prefix adder.

• To Developed the Application Architecture of MDCLCG method with using Proposed Three Operand Adder and proved the performance of area, delay and power.

• Modelsim
• Xilinx

Proposed System:

The basic functional unit for performing modular arithmetic in different cryptography and pseudorandom bit generator (PRBG)  algorithm is the method of three operand binary adder. The commonly used technique to execute the three operand extension is the carry save adder (CS3A). The ripple carry step in the CS3A, however, the result in a significant delay in the propagation of O(n). In addition, a two operand adder of parallel prefix method such as Han-Carlson (HCA) can also be used for three operand addition, which decreases the critical path latency at the expense of additional hardware considerably. Therefore, using pre-compute bitwise addition followed by carry prefix computation logic, a modern high speed and space efficient adder architecture is proposed to perform the three operand binary addition that consumes significantly less area, low power and dramatically decreases the adder delay to O (log2 n). The proposed architecture of this work will developed at 8-bit, 16-bit and 32-bit three operand adder with using kogge stone parallel prefix adder, and developed the application of MDCLCG method with using Proposed Three Operand Adder and proved the performance of area, delay and power.

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High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder