Proposed Title :
Utilizing three separate techniques with hybrid protection, the FPGA implements a locked and obscured FIR filter architecture.
Improvement of this project :
To design Obfuscated and Locked FIR Filter design using three different technique of Direct form, Transpose form, Folded form.
Each form designed with three different architectures such as MUL, SA and CRK.
To reduced logic gates of proposed approach, of this Obfuscated FIR Filter design with XOR MUX Full adder design instead of Conventional Full adder design.
A digital finite impulse response (FIR) filter is a common building component in digital signal processing applications, and its behavior is defined by its coefficients. In order to hide filter coefficients from an attacker, efficient obfuscation approaches have been proposed, either by hiding them behind decoys or by substituting them with key bits. In this article, we initially introduce a query attack that can discover the secret key of such obfuscated FIR filters, which could not be broken by the existing prominent attacks. Then, we propose a first of its kind hybrid technique, including both hardware obfuscation and logic locking using a point function for the protection of parallel direct and transposed forms of digital FIR filters. Experimental results show that the hybrid protection technique can lead to FIR filters with higher security while maintaining the hardware complexity competitive or superior to those locked by prominent logic locking methods. To reduce the hardware complexity, this paper proposed approach of arithmetic operation design with XOR-MUX full adder, to reduce the number of logic gates in FIR filter architecture. It is also shown that the protected multiplier logic blocks and FIR filters are resilient to existing attacks. The results on different forms and realizations of FIR filters show that the parallel direct form FIR filter has a promising potential for a secure design.
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Hybrid Protection of Digital FIR Filters
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