Proposed Title :
Low Power and High Speed Implementation of FIR Filter Design using CMOS Truncated Multiplier with 10T GDI Full Adder
Improvement of this Project:
- CMOS GDI adder using Truncated MultiplierDesign of FIR-8 TAP Filter with using CMOS Truncated Multiplier
- Tanner EDA
In the proposed system of Digital signal processing with Filtering technique of Finite impulse response is widely used in many applications such as audio signal based filtering, video/image based filtering, and signal transmission and reception, high frequency noise reduction, echo cancellation and various communication based application, including highly configurable design of software define radio (SDR). The main priority of this FIR filter design is Delay, Multiplier and adder, here the existing system will have used MCM (Multiple constant multiplication) and Normal adders in the architecture design, it will take more area and more power consumption, and also low performance in signed and unsigned multiplication and addition with carry operation. So in this proposed work to modified the multipliers and adders in the FIR Filter design. Multipliers to be replaced to Truncated with GDI (Gate Diffusion Input) full adder, based upon this modification our performance will increases better than existing results. In recent technology of any application, adders is a more priority to do a function and task of arithmetic operation, in crucial this adder based arithmetic operation will decide the logic size, propagation delay, power of applications, based upon this improvement the adder design logic size will reduced year by year, here a proposed work of this paper will design using a single bit full adder to design a multiplier. In this multiplier design, adder is a main priority to reduce the arithmetic logic size and increases speed of multiplier, in recent we have lots of multiplier design, Vedic multiplier, Wallace tree multiplier, booth multiplier, approximate multiplier.
Here, the proposed work will taken truncated multiplier design, it’s because, the truncated multiplier will have a capability to reduced internal and external architecture size in every design, regarding this truncated multiplier will have three options such as rounding, deleting, truncating, here the MSB bits will be truncated and present the output of n x n multiplication will provided only n bit level, using this truncated multiplier the proposed work will designed a 8-Tap FIR(Finite impulse response) filter and shown the efficiency of filter design using this CMOS GDI (Gate Diffusion Input) adder design. This proposed work will design in CMOS Logic gate and which 10-T transistor level of full adders with 90um technology, finally proved the terms of area, delay and power.
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Low Power and High Speed Implementation of FIR Filter design using CMOS GDI Truncated Multiplier
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