Proposed Title :

A 45 nm CMOS Implementation of Soft Error Aware Read Stability 12T SRAM for Multi Node Upset Recoverability

Improvement of this project :

• To design this 12T Soft-Error-Aware Read-Stability-Enhanced SRAM at 65nm and 45nm CMOS technology and proved the comparisons of area, delay and power.

• To extend this 12T Soft-Error-Aware Read-Stability-Enhanced SRAM up to 8-bit and designed at 65nm and 45nm CMOS Technology and proved the comparisons of area, delay and power.

Software implementation:

• Tanner EDA

Proposed System:

Read Stability Enhancement for Soft Error Low-Power 12T SRAM with Multi-Node Upset Recoverability  of individual transistors and the space that between them are rapidly shrinking as a direct result of advances in technology. If a radiation particle were to impact a sensitive node of a conventional 6T SRAM cell, the data that were stored in the cell would be flipped, which would result in a single-event upset (SEU). The authors of this work suggest a Soft-Error-Aware Read-Stability-Enhanced Low Power 12T (SARP12T) SRAM cell as a means of reducing the probability of SEUs occurring. Comparisons are made between SARP12T and other recently disclosed soft-error-aware SRAM cells. This allows for an assessment of the relative performance of SARP12T. In addition to these benefits, the proposed 12T SRAM cell having maximum level of read stability, it will compared to majority of the existing SRAM cells have lower write ability, however SARP12T has both a greater write ability and a shorter write latency. All of these enhancements to the proposed cell may be accomplished by having a read latency that is just marginally longer and by having a read and write energy consumption that is marginally greater. To design this 12T Soft-Error-Aware Read-Stability-Enhanced SRAM at 65nm and 45nm CMOS technology and to extend this 12T Soft-Error-Aware Read-Stability-Enhanced SRAM up to 8-bit and designed at 65nm and 45nm CMOS Technology and proved the comparisons of area, delay and power using Tanner EDA Tool.

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Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications