Proposed Title :

Design the ECG-FIR Filter Design using Multiple Constant Multiplication at Minimal Hardware Cost

Improvement of this project :

• To design the 8^th order ECG FIR Filter design using Proposed Multiple Constant Multiplication with Minimal Hardware Cost.

• Design the Multiple Constant Multiplication for different coefficient with normal and truncated MCM with XOR-MUX Full Adder.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

Multiple Constant Multiplication (MCM) over integers is a frequent operation requiring highly optimized hardware in the design of VLSI systems. A multiplier-less circuit is an efficient method for replacing costly generic multiplication with bit-shifts and additions. In this paper, we enhance the current optimal approach for MCM, which is based on Integer Linear Programming. We introduce a new low-level hardware cost metric based on the number of one-bit adders and demonstrate that it correlates strongly with the number of LUTs. This new model enabled us to evaluate intermediate truncations that allow significant resource savings when full output precision is not necessary. We incorporate error propagation principles into our Integer Linear Programming model in order to guarantee a user-specified error bound for MCM results. The proposed ILP models for multiple variants of MCM are implemented as an ECG 8^th order FIR Filter design. We conduct extensive experiments to evaluate our models and propose an in-depth analysis of the effect of design metrics on synthesized hardware, and analysis the area, delay and power.

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Toward the Multiple Constant Multiplication at Minimal Hardware Cost