Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
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Source Code : VHDL
Abstract:
In information theory, a low-density parity-check (LDPC) code is a linear error correcting code, a method of transmitting a message over a noisy transmission channel. An LDPC is constructed using a sparse bipartite graph. LDPC codes are capacity-approaching codes, which means that practical constructions exist that allow the noise threshold to be set very close (or even arbitrarily close on the BEC) to the theoretical maximum (the Shannon limit) for a symmetric memory-less channel. The noise threshold defines an upper bound for the channel noise, up to which the probability of lost information can be made as small as desired. Using iterative belief propagation techniques, LDPC codes can be decoded in time linear to their block length.
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Proposed System:
- Here we are implementing the LDPC in NAND Flash memory deteriorates due to multi-level cell technique and advance manufacturing technology. To deal with more errors, LDPC codes show superior performance to conventional BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chip memory cost and high-throughput demand. This paper presents a byte-reconfigurable cost-effective high-throughput QC-LDPC codec design for NAND Flash memory systems. Reconfigurable codec design is proposed to support various QC- DPC codes for different Flash memories. To save on-chip memory cost, shared-memory architecture and rescheduling architecture are presented for encoder and decoder, respectively.
Advantages:
- Efficiency Increased
- High speed
- Low power consumption
Software Implementation:
- Modelsim 6.5b
- Xilinx 14.2
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