High radix Booth encodings provide significant decrease on the number of partial products in the multiplication. However, due to the generation on hard multiples, additional delay and power are incurred, which in turn hampers the use of high radix Booth encodings. In this brief, an approximate radix-256 Booth encoding is proposed to circumvent the generation on hard multiples. A partial encoding approach is used to produce partial product pairs, which can be obtained easily by simple shifting and complementing operations. The exact encoding values are thus replaced by the sum of each corresponding partial product pair. A 16 × 16-bit multiplier with proposed approximate radix-256 Booth encoding has been implemented for performance evaluation. Compared with the traditional radix-4 Booth encoding multiplier, the proposed design achieves 42.39%, 7.03%, 26.00% reduction in area, delay, and power, respectively. Additionally, 2-D discrete cosine transform (DCT) system with proposed multiplier is demonstrated as an application. 33.51% and 24.15% reduction on area and power consumption are obtained respectively with a penalty of 6.42dB peak signal to noise ratio loss in average when compared with the traditional design.
Software Implementation:
Modelsim
Xilinx
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Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing
