NXFEE Innovation will have more than ten years of experience in Semiconductor IP Development in this field of research. Our organisation will be knowledgeable about Semiconductor IP Products and Application Related Products, as well as a wide range of solutions such as custom ASIC/FPGA/DSP/EMBEDDED System/Wireless Technologies.
We have a highly qualified R&D unit for Wireless/Embedded/FPGA/ASIC Design. Our sound technology and knowledge base have assisted us in developing products that use emerging technologies such as FPGA, VHDL, VERILOG HDL, SYSTEM VERILOG HDL, UVM, OVM, VVM, DSP, RTOS, DSP, Bluetooth, WI-Fi, RF, CDMA, and others in the areas of Industrial Automation, Telecommunications, Consumer Electronics, and Automotive Applications.
Development Products & Research on:
High Speed Data Transmission
Secure Video Processing
Secure Digital Demodulation
Signal Processing and Applications
NXFEE Ph.D Procedure Detailed
Step 1 : Select a Research Topic or Related IEEE Journal Article ( NXFEE can given three different research paper for your Research Topic ).
Step 2 : Once a Topic or Existing Journal Paper has been selected based on your interest, we must begin writing a Feasibility Document for research and inspiration. ( NXFEE Given a Feasibility Idea document in Free of Cost, but for Ph.d conformation we are charging Rs.5000/-, this amount we can reduce in future payments )
Step 3 : Once got conformation from Feasibility Idea Document, We can Start a Proposal Document ( But some persons not required proposal document, they start a work directly as per guide advice ). NXFEE given a proposal document with ( For Proposal Document writing NXFEE charging Rs.20,000/-, if not required proposal we can start the work directly as per your requirements)
Step 4 : Once completed proposal document we can get a idea, now we can start a development, before that we need to plan for number of publications. For Development also we need to plan, required hardware output or only simulations. As per this commitment from your end, NXFEE can start the development and Write up. ( For Development we are not charging a full amount, you can pay the amount by module by module )
Step 5 : Development Module 1 Completion (Also Possible for Publication )
Step 6 : Development Module 2 Completion (Also Possible for Publication )
Step 7 : Development Module 3 Completion ( Also Possible for Publication )
Step 8 : Development Module 4 Completion (Also Possible for Publication )
( Pay Initial Amount and Get Feasibility Idea Within 3 Days )
( For this initial registration we will provide one page novelty based feasibility abstract document with comparisons and publication details — This amount will less on future payment – we will accept to be re-modified this initial proposed document up to the conformation from your institution )
Do your Ph.D in Installment (Module By Module) – Not need to Pay Partial or Full Amount for Whole Ph.D
( We can partition the work and the charges.) You can pay the money module by module; you are not required to pay the whole amount or 50% of the total fee for your Ph.D. Once you are happy with the first module’s work, you may go on to the second module, which will reduce your burden and improve trust. The same would be true for the publication process; the first article will be prepared, and publication will be completed. You can pay the same amount for the second and third papers. )
In this novelty approach of Scalable approximate multiplier with using truncated rounding based technique which presents to reduced a number of partial products which based on leading one bit position. In the approximate signed multiplication design is performed with using arithmetic unit, truncation unit, absolute unit for shift and add accumulation. In this operation of TOSAM will have number of modes it will differentiate based upon height (h) and truncated (t) such as (h,t) it will described in the architecture TOSAM(0,2), TOSAM(0,3), TOSAM(1,5), TOSAM(2,6), TOSAM(3,7), TOSAM(4,8), TOSAM(5,9). Here this will contain more absolute error in the LSB data shift Unit, thus proposed methodology will modified all the arithmetic operations of shift and add unit with using XOR-MUX Full adder to find a better solution and reduced the absolute error and it will proved with higher improvements of area and energy consumptions. In this proposed novelty work will modified approximate signed multiplier architecture as per absolute error reduction. Finally this work will designed in Verilog HDL and simulated in Modelsim, Synthesized in Xilinx 14.2.
In a recent technology of digital image processing along with multimedia images based transmission and reception while taking more complexity and image disordering positions in contribution on image encryption and decryption method thus now a day’s increasing private protect contained information in image processing. Here this proposed work will introduced a one way encryption and decryption technique using magic square regarding to reduced the complexity and image disordering with good lattice point. This magic square algorithm will have number of integer based summations on rows and columns via n x n matrix, due to this arithmetic operation such as addition, subtractions and multiplication it will take more memory logic element and garbage signals, here this proposed work will introduced novel method of reversible magic square algorithm using reversible logic gates such as PERES, FEYMAN, FREDKIN and so on. Therefore, in this magic square algorithm will get very less memory logic element and garbage signal and also get more efficient in image encryption technique. Furthermore, this image encryption and decryption method will proved with Mammography Images because its most effective method for early detection of routine breast cancer screening among mass classifications. Finally this work will integrated in Verilog HDL, Simulated in Modelsim and Synthesized in Xilinx FPGA, and also compared all the parameters in terms of area, delay and power.
To design a Real time detection of symptomatic pattern using audio biological signal based on wearable health monitoring system with low power and efficacious. Now a day’s digital audio recording will using for many application with advantages, here it will used to find out patient symptoms, such as cough, sneeze, vomiting, wheezing, belching and so on. In this research, we are designed a novel GDI (Gate Diffusion Input) based Full adder design of HSCG-SCS (Half Sum Carry Generation – Sum Carry Selection) unit, it will proved in back-end with tested 22nm CMOS Technology and hence proved minimum number of CMOS Gates with compared to reversible logic Full adders (Fredkin, Feynman, HNG, PERES, SGG, Toffoli, TSG). In Second part using this proposed full adder to design a Efficient Truncation Multiplier in Front-End VHDL with provide comparisons (HSCG-SCS adder using Truncation Multiplier, RCA adder using Truncation Multiplier, CSLA SQRT adder using Truncation Multiplier, CBL adder Using Truncation Multiplier, RCA-BEC adder using Truncation Multiplier). In Third Part using this HSCG-SCS Truncation Multiplier and HSCG SCS adder to design a FIR Filter Design, and hence proved comparisons with all adders and Multipliers. In Forth part, using this FIR filter, proposed Multiplier, proposed adder to design DWT and also developed a application oriented work in Real time detection of Audio Biological System its included with (DWT, DCT, Energy, Cost-line, QA, Mel Filter, etc.,) and Finally published this all works.
In recent years of innovative technology grow as application products in medical domain to support human problems to identification, rectification and alert a persons, as per this domain a wearable device will taken more priority to identify the human problems such as heart attacks, fewer, seizure prediction, wheezing, etc. In this application to characteristics a human body channel communication (BCC), to transmit and receive the data in long distance of communication, to alert the related persons and doctors regarding to monitor the patient at time by time of communication. In the exiting wearable devices will using a human body skins as transmission and reception medium, its affect the human freedoms, and create more jitter noise, the transmission and reception medium of body channel communication will not having fastest speed and does not transmit the data in high accuracy, to overcome these problems the proposed method will designed in Wearable device of Body Channel Communication with technique of DQPSK modulation. As per this application this paper proposed a novel design of Wearable device using Body channel communication to take the parameters of ECG, EMG, Temperature and Pressure, this parameter will transfer through DQPSK Modulation with encoding and decoding technique. In the Wireless network based communication of interconnection methodology will support high bandwidth and long range of communication, as per this Differential Quadrature phase shift keying (DQPSK) will provide the same data as throughput and less bandwidth which is compare to other modulation scheme such as BPSK, BFSK, QPSK. This Wearable device module will need a Encryption and Decryption technique to send the data securely, as per the digital data signal transmission line, a process of encoding and decoding is chosen in this proposed work to avoid signal overlap, signal distortion with signal interference, so proposed work will have implemented with line coding method. In the line coding method will support more number of bits transmission and reception in less bandwidth, more power efficiency and it will also support probability of error reduction. Here, we have compared the encoding technique in such as, NRIZ, RZ UNI-Polar, RZ BI-Polar and Differential Manchester method in wireless communication of DQPSK Modulation with 4, 8, 16 Quadrant using Wearable device of Body Channel Communication Decoding Method of ECG and EMG will predicting Arrhythmia attacks and record intervals trough UART Interface using four steps such as ECG-EMG Filtering, PQRST Delineation with help of PAT Algorithm, Feature Extraction and Classification. Finally the proposed work will design in VHDL language and synthesized using MAX10 Altera Quartus FPGA, with BER Testing and also shown the output comparison of area, delay and power.
In a recent technology of System on Chip, which have more integrate a variety of different IP cores, and it will have test sequence to store and generate a original data in encode and decode method. Now a days in digital communication a encoding and decoding method will have lot of data losses, potential faults and bit error losses in signal transmission and reception, due to distortion, jitters, and fluctuations. To overcome this problem, the System on Chip introduce a test data compression method, which have reduce complexity, time and cost in Design for testability and code compression technique, to test a data at encoded in off-line and decode in on-line with help of Automatic Test Pattern Generation (ATPG) method. In this test data compression has focused on run-length coding, which have drawbacks to test data in sequence of zeros, and terminated by ones, to overcome this problem Alternating statistical run-length coding(ASRL), and dictionary based coding was introduced. Here, the proposed work will tested to highest ratio in compression technique, which have a encoded scheme will designed ASRL followed by dictionary based method, and decoded vice-versa, based upon this a test ration will increases, and reduced data loses, potential faults and bit error loses, this method shown as a experimental result in XILINX FPGA using Verilog HDL, and finally shown a comparison in terms of area, power and delay with compression ratio.
In recent technology adders and subtraction is most priority design to decide a area, delay and power in all digital design applications, because a single adder and subtraction will decide logic size of a Multipliers and dividers. These adder, subtraction, multiplication and division will decide all digital design applications, based upon this research here a author decide a Adiabatic logic adder designs because adiabatic logic is most efficient power consumption logic compared to all other adder design. In this research work, will compared adiabatic logic in such as ECRL, 2N-2P, 2PASCL, PFAL, PAL. Here using this adiabatic logic to design and Full adder in 22nm, 32nm, 45nm CMOS Technology and find out the good power consumption, and hence proved the same technique in different adders such as Ripple Carry Adder, Carry Select Adder, Carry Save Adder, Carry Look ahead Adder, Kogge Stone Adder with design in CMOS Technology. Finally compared with all this works in Tanner EDA with successfully published this work.
In a recent research in Super resolution technique to increases a resolution in single image super resolution to generate a higher image super resolution. This paper presents briefly real time super resolution method of FHD ( Full HD) images without using a Frame buffer. In the existing method of super resolution technique presents in nearest neighbor, linear, cubic, bilinear methods which using low resolution image input using only number of line buffers. This paper presents a real time system of Super resolution technique in without a frame buffer using Bi-Cubic interpolations, Where Bi-Cubic interpolation is used for reconstruction the low frequency image to High frequency images, these Bi-Cubic interpolation will have capability to interpolate sixteen nearest neighbor of a pixel. In this paper additionally resolves high frequency patches, with overlapped to construct super resolutions images with using kernel algorithm. These Operations for gaining a high frequency results are applied to the Y-luminance channel only. While the high resolution Cb and Cr Channels are generated by Bi-Cubic Interpolations. The proposed System generates the output image at 1600×1600 size from 800×800 image size. This output of Image Super resolution 1600×1600 will given to Wavelet Filter and Wiener Filter to reduce a Image Denoising, and apply with motion estimation of Block Matching algorithm with 3D Filtering, and finally its decide with multiplier fames based super resolutions and hence proved in PSNR and SSIM. This image enhancement of Super resolution technique is implemented in VHDL and Synthesized in Xilinx Vertex-5 FPGA and Shown the Comparison of Area, Delay and Power.
In this technique of LECTOR and MTCMOS based CMOS design can decrease the complexity of leakage current and power dissipation as well as decimate the delay of logic circuits while gate or sleep transistor in active region. In LCT which is leakage control transistor (LECTOR) controlled by another source. About MTCMOS based CMOS logic gates are provides low leakage by using high threshold voltage (Vt) sleep transistors. In existing system, NAND gate is designed with the help of above two technique and its simulated with CMOS technology. From MTCMOS, which is designed with gating transistors for reducing delay of power gated circuits during active mode. In proposed system designed with 16 bit multiplier using LECTOR and MTCMOS method using NAND Gate and its tested with 65nm and 90nm CMOS technology at various supply voltage ( 1.1V, 1.2V, 1.3V, 1.4V, 1.5V, 1.6V,..). This multiplier is developed using Half adder and Full adder with using NAND based LECTOR and MTCMOS technique. Thus the results indicates an leakage voltage reduction. This Design is implemented in Tanner EDA and proved comparison of DC analysis, area and power.
This paper presents a FPGA Implementation of mixed pipelined architecture and parallel processing for Deblocking filter and SAO architecture in High Efficiency Video coding (HEVC) standard. In this paper aims to developed HEVC architecture in low latency with increase throughput and reduce the number of processing cycles with using Edge filtering method of modified Horizontal and Vertical Boundaries. This proposed work will presents mixed pipeline architecture and conditions based filter decisions with multiple coding tree units on size 64×64, 8×4 32×32, 4×8, block sizes. This proposed work is implemented on Field Programmable Gate Array (FPGA) platforms and compared with state of the literature and conclude the proposed work with 64×64 block size is suitable for all consumer High Definition applications, finally this design developed in Verilog HDL and synthesized in Xilinx Vertex FPGA XC5VFX200T-2FF1738 and compared all the terms of area, delay and power.
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