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2020

IEEE Transactions on VLSI 2020

Showing all 13 results

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A Compact 0.3 V Class AB Bulk Driven OTA
~~₹8,000.00~~ ₹5,000.00
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A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications
~~₹12,000.00~~ ₹8,000.00
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Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
~~₹15,000.00~~ ₹10,000.00
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Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
~~₹16,000.00~~ ₹10,000.00
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ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
~~₹18,000.00~~ ₹10,000.00
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FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
~~₹18,000.00~~ ₹12,000.00
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High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder
~~₹20,000.00~~ ₹16,000.00
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One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
~~₹10,000.00~~ ₹6,000.00
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Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications
~~₹12,000.00~~ ₹8,000.00
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RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory
~~₹25,000.00~~ ₹16,000.00
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Sparse FIR Filter Design via Partial 1-Norm Optimization
~~₹15,000.00~~ ₹10,000.00
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The Mesochronous Dual-Clock FIFO Buffer
~~₹12,000.00~~ ₹8,000.00
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Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System
~~₹12,000.00~~ ₹6,000.00
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A Compact 0.3 V Class AB Bulk Driven OTA

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory

Sparse FIR Filter Design via Partial 1-Norm Optimization

The Mesochronous Dual-Clock FIFO Buffer

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System