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2020

VLSI Research Transactions – 2020

Showing all 22 results

Sale!
A Compact 0.3 V Class AB Bulk Driven OTA
~~₹8,000.00~~ ₹5,000.00
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A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA
~~₹20,000.00~~ ₹12,000.00
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A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process
~~₹18,000.00~~ ₹12,000.00
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A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications
~~₹12,000.00~~ ₹10,000.00
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A Review on Fundamentals of Ternary Reversible Logic Circuits
~~₹18,000.00~~ ₹12,000.00
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A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers
~~₹10,000.00~~ ₹6,000.00
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AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
~~₹20,000.00~~ ₹15,000.00
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Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
~~₹15,000.00~~ ₹10,000.00
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Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
~~₹16,000.00~~ ₹10,000.00
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Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs
~~₹25,000.00~~ ₹16,000.00
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Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration
~~₹16,000.00~~ ₹12,000.00
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Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation
~~₹12,000.00~~ ₹6,000.00
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ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
~~₹18,000.00~~ ₹10,000.00
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FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
~~₹18,000.00~~ ₹12,000.00
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High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder
~~₹20,000.00~~ ₹16,000.00
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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
~~₹16,000.00~~ ₹8,000.00
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One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
~~₹10,000.00~~ ₹6,000.00
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Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications
~~₹12,000.00~~ ₹8,000.00
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RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory
~~₹25,000.00~~ ₹16,000.00
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Sparse FIR Filter Design via Partial 1-Norm Optimization
~~₹15,000.00~~ ₹10,000.00
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The Mesochronous Dual-Clock FIFO Buffer
~~₹12,000.00~~ ₹8,000.00
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Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System
~~₹12,000.00~~ ₹6,000.00
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A Compact 0.3 V Class AB Bulk Driven OTA

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

A Review on Fundamentals of Ternary Reversible Logic Circuits

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory

Sparse FIR Filter Design via Partial 1-Norm Optimization

The Mesochronous Dual-Clock FIFO Buffer

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System