Proposed Title :
A 16nm Low Power CMOS Implementation of AND, OR, XOR based 1-Bit Hybrid Full Adder Design
Improvement of this Project:
To design the 1-bit Hybrid Full adder design at 22nm and 16nm CMOS Technology.
- Tanner EDA
This paper introduce a novel low power 1-bit hybrid full adder architecture based on pass transistor (PTs), Transmission Gate (TGs), and conventional complementary metal oxide semiconductor (CCMOS) logic. These adders are essential components in digital and VLSI system. Arithmetic operations are critical components of digital systems. This proposed architecture is realized by many types of logic systems, each of which plays a particular function in the hybrid system. In this structure, a hybrid full adder cell with one bit implemented using 22nm CMOS Technology and 16nm CMOS Technology. This proposed method of hybrid full adder architecture will more suitable for recent high speed central processing units and all digital VLSI Systems. This work was designed in Tanner EDA tool, and this design outperforms proved in terms of power consumptions and latency in very low level.
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Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology
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