Proposed Title :
A 45nm CMOS Implementation o Successive Approximation ADC using SMTCMOS Method at 1.2 V
Improvement of this Project:
To design the Successive Approximation SMTCMOS method at 45 nm and 65 nm CMOS Technology and compare all the parameters in terms of area, delay and power.
- Tanner EDA
Low power at 1.2 V efficient successive approximation register of the analog to digital converter using D FF with support of switched multi threshold complementary metal oxide semiconductor (SMTCMOS), its utilizing with principled open loop comparator (POLC). During high proficiency and low power application of SAR ADC is becoming more and more known, but the impacts of resolution and speed limitation are unfavorable one. A systematic technique of low power SAR ADC based on POLC method has been presented in order to solve the aforementioned problem, its taking into resolution reflecting. This proposed work of POLC method reduces the propagation time, and power consumptions A SMTCMOS process of D flip flop also taken low energy consumptions. Finally this work developed in Tanner EDA at 45 nm and 65 nm CMOS Technology and compared all the terms of area, delay and power.
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A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications
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