Proposed Title :
CMOS Implementation of 45nm with 40Gb/s MUX -DEMUX Transformer Coupled Technique
Proposed System:
This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. The MUX and the DEMUX chips are fabricated in 45-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with 43.2 milliwatts power consumption.
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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface
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