## Description

**Existing System:**

**DFG Transformation:**

Transformation is to modify a given DFG, while preserving the functionality of the original DFG. A transformed DFG usually yields a different hardware structure, which leads to a different structure for testability and power consumption. Following techniques are available for a behavioral transformation of DFGs:

- Algebraic laws and redundancy manipulation:

Associativity, commutatively, and common sub-expression

- Temporal Transformation:

Retiming, pipelining, and rephrasing

- Control (Memory) Transformation:

Loop folding, unrolling, and functional pipelining

- Sub-Operation level Transformation:

Add/shift multiplication and multiple constant multiplications

Among the above techniques, pipelining and loop folding/unrolling are most commonly used and are described in detail. There are two types of pipelining, structural pipelining and functional pipelining, which are also explained below.

**Structural Pipelining**

Pipelined modules are used in structural pipelining. If there is no data dependency exists between the operations and the operations (which implies they do not start in the same control step), pipelined modules can be shared, even if the corresponding operations overlap in their executions. For example, suppose that a pipelined multiplier resource, with execution delay of 2 and a data introduction interval of 1, is available. Then we can have a data flow graph with pipelined multipliers. Note that operations v6, v7, and v8 can share one pipelined multiplier.

**Functional Pipelining**

In a functional pipelining, it is assumed that there is a constraint on the global data introduction interval d0 representing the time interval between two consecutive executions. The number of required resources in pipelined implementations depends on d0. The smaller d0 is, the larger the number of operations executing concurrently. The result of the scheduling, using two stages and data introduction interval of two time steps, operations in the stage 1 and stage 2 are executed concurrently and cannot be shared.

**MCM-Based Implementation of Fixed-Coefficient FIR Filter:**

Critical path and shortest path solving contribute to most of the computation time in retiming.

**Definition 1 (the path solver problem):** Let, S= {s_{0},s_{1},s_{3},….,s_{k}} where is the maximum number of feasible solutions available for retiming of a considered filter DFG. During retiming of digital filters in high level synthesis, the shortest path between the nodes must be computed for (K+1) times where is the number of feasible solutions available for the DFG which is nothing but unique entries in path delay matrix. Similarly, the critical path must be computed for (K+1) . General purpose processors (GPPs) where retiming algorithm is implemented are fully programmable but are less efficient in terms of power and performance. Hence, the problem is to improve the performance and power of retiming using FPGA based path solvers.[6][17] Further, along with retiming, high level transformation technique called automatic pipeline is applied to improve the filter speed.

**Definition 2 (multiple constant multiplication in digital filters):** For the considered filter coefficient constant in the retimed filters, find the set of multipleirless operations(O_{1},O_{2},O_{3},…O_{n}) with minimum number of addition, subtraction, and shift operations using multiple constant multiplier architecture to optimize the filter architecture further.

**Definition 3 (optimization and automation of filter HDL)**: An environment needs to be developed to obtain HDLs of retimed filters in which user can choose different data path element architectures depending on the specifications. This reduces time to market and helps to evaluate a lot of hardware implementation trade-offs. Filter equivalence checking after applying high level transformation needs to be done which needs to be developed as a part of the optimization environment.

**Proposed System:**

**Phase 1:**

In phase 1 to discussed about 16 tap FIR filter for Low pass, High pass, Band pass, and band stop filter and to analysis the performance, efficiency, speed, and power consumption for the respective filter types. Fig.6 shows the block diagram of the proposed system. The NCO used for signal generation with required frequency range. NCO is used in the modulation block.

**Phase 2:**

To replace 16 tap FIR filter to 32 tap FIR filter and compare the both filter performance, accuracy, and power consumption.