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Area Efficient

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Sale!
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
~~₹7,000.00~~ ₹6,000.00
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Sale!
A 65-nm CMOS Constant Current Source With Reduced PVT Variation
~~₹12,000.00~~ ₹6,000.00
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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
~~₹10,000.00~~ ₹7,000.00
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Sale!
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹35,000.00~~ ₹15,000.00
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Sale!
A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA
~~₹20,000.00~~ ₹15,000.00
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Sale!
A Floating-Point Fused Dot-Product Unit
~~₹15,000.00~~ ₹10,000.00
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Sale!
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process
~~₹15,000.00~~ ₹10,000.00
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Sale!
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace
~~₹35,000.00~~ ₹20,000.00
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Sale!
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)
~~₹10,000.00~~ ₹7,000.00
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Sale!
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹15,000.00~~ ₹9,000.00
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Sale!
A Review on Fundamentals of Ternary Reversible Logic Circuits
~~₹14,000.00~~ ₹10,000.00
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Sale!
A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
~~₹10,000.00~~ ₹7,000.00
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Sale!
A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
~~₹15,000.00~~ ₹10,000.00
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Sale!
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
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Sale!
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
~~₹10,000.00~~ ₹7,000.00
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Sale!
An Efficient Design for Reversible Wallace Unsigned Multiplier
~~₹16,000.00~~ ₹8,000.00
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Sale!
An Efficient Implementation of Floating Point Multiplier
~~₹20,000.00~~ ₹14,000.00
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Sale!
An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
~~₹15,000.00~~ ₹10,000.00
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Sale!
Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
~~₹14,000.00~~ ₹10,000.00
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Sale!
Area Delay Power Efficient Carry Select Adder
~~₹10,000.00~~ ₹5,000.00
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Sale!
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
~~₹15,000.00~~ ₹10,000.00
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Sale!
ASIC design of UHF RFID reader digital baseband
~~₹12,000.00~~ ₹6,000.00
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Sale!
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
~~₹10,000.00~~ ₹7,000.00
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Sale!
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
~~₹16,000.00~~ ₹12,000.00
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Sale!
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
~~₹16,000.00~~ ₹10,000.00
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Sale!
Concept Design and Implementation of Reconfigurable CORDIC
~~₹15,000.00~~ ₹10,000.00
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Sale!
Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs
~~₹25,000.00~~ ₹16,000.00
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Sale!
Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems
~~₹10,000.00~~ ₹6,000.00
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Sale!
Design of Testable Reversible Sequential Circuits
~~₹10,000.00~~ ₹4,000.00
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Sale!
Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic
~~₹20,000.00~~ ₹14,000.00
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Sale!
Efficient Design for Fixed-Width Adder-Tree
~~₹20,000.00~~ ₹12,000.00
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Sale!
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
~~₹18,000.00~~ ₹10,000.00
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Sale!
Error Detection and Correction in SRAM Emulated TCAMs
~~₹20,000.00~~ ₹15,000.00
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Sale!
Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator
~~₹25,000.00~~ ₹12,000.00
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Sale!
FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
~~₹18,000.00~~ ₹12,000.00
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Sale!
FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
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Sale!
Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications
~~₹15,000.00~~ ₹9,000.00
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Sale!
Graph-Based Transistor Network Generation Method for Supergate Design
~~₹10,000.00~~ ₹4,000.00
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Sale!
High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
~~₹12,000.00~~ ₹7,000.00
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Sale!
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop
~~₹8,000.00~~ ₹4,000.00
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Sale!
High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder
~~₹16,000.00~~ ₹12,000.00
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Sale!
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
~~₹18,000.00~~ ₹12,000.00
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Sale!
Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology
~~₹10,000.00~~ ₹6,000.00
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Sale!
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
~~₹16,000.00~~ ₹12,000.00
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Sale!
Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
~~₹15,000.00~~ ₹9,000.00
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Sale!
Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA
~~₹10,000.00~~ ₹6,000.00
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Sale!
Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹7,000.00
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Sale!
Low Power Variation Tolerant Nonvolatile Lookup Table Design
~~₹10,000.00~~ ₹7,500.00
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Sale!
Low-Cost and Programmable CRC Implementation Based on FPGA
~~₹15,000.00~~ ₹10,000.00
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Sale!
Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
~~₹10,000.00~~ ₹7,000.00
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Sale!
New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata
~~₹15,000.00~~ ₹10,000.00
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Sale!
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
~~₹10,000.00~~ ₹6,000.00
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Sale!
Obfuscating DSP Circuits via High Level Transformations
~~₹10,000.00~~ ₹7,000.00
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Sale!
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
~~₹10,000.00~~ ₹8,000.00
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Sale!
Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding
~~₹10,000.00~~ ₹6,000.00
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Sale!
Quaternary Logic Lookup Table in Standard CMOS
~~₹10,000.00~~ ₹6,000.00
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Sale!
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
~~₹10,000.00~~ ₹6,000.00
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Sale!
Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array
~~₹20,000.00~~ ₹12,000.00
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Sale!
Sharing Logic for Built In Generation of Functional Broadside Tests
~~₹10,000.00~~ ₹4,000.00
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Sale!
Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders
~~₹18,000.00~~ ₹12,000.00
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Sale!
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
~~₹16,000.00~~ ₹8,000.00
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Sale!
The Mesochronous Dual-Clock FIFO Buffer
~~₹12,000.00~~ ₹8,000.00
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Sale!
Towards Efficient Modular Adders based on Reversible Circuits
~~₹16,000.00~~ ₹10,000.00
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Sale!
VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
~~₹12,000.00~~ ₹8,000.00
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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

A Floating-Point Fused Dot-Product Unit

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

A Review on Fundamentals of Ternary Reversible Logic Circuits

A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

An Efficient Design for Reversible Wallace Unsigned Multiplier

An Efficient Implementation of Floating Point Multiplier

An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

Area Delay Power Efficient Carry Select Adder

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

ASIC design of UHF RFID reader digital baseband

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

Concept Design and Implementation of Reconfigurable CORDIC

Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

Design of Testable Reversible Sequential Circuits

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

Efficient Design for Fixed-Width Adder-Tree

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Error Detection and Correction in SRAM Emulated TCAMs

Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

Graph-Based Transistor Network Generation Method for Supergate Design

High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA

Low Power Divider Using Vedic Mathematics

Low Power Variation Tolerant Nonvolatile Lookup Table Design

Low-Cost and Programmable CRC Implementation Based on FPGA

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

Obfuscating DSP Circuits via High Level Transformations

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

Quaternary Logic Lookup Table in Standard CMOS

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

Sharing Logic for Built In Generation of Functional Broadside Tests

Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

The Mesochronous Dual-Clock FIFO Buffer

Towards Efficient Modular Adders based on Reversible Circuits

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding