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Area Efficient

Showing 1–16 of 44 results

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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
~~₹7,000.00~~ ₹6,000.00
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A 65-nm CMOS Constant Current Source With Reduced PVT Variation
~~₹12,000.00~~ ₹6,000.00
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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
~~₹10,000.00~~ ₹7,000.00
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A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹20,000.00~~ ₹15,000.00
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A Floating-Point Fused Dot-Product Unit
~~₹15,000.00~~ ₹10,000.00
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A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)
~~₹10,000.00~~ ₹7,000.00
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A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹15,000.00~~ ₹9,000.00
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A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
~~₹10,000.00~~ ₹7,000.00
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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
~~₹10,000.00~~ ₹7,000.00
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An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
~~₹15,000.00~~ ₹10,000.00
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Area Delay Power Efficient Carry Select Adder
~~₹10,000.00~~ ₹5,000.00
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ASIC design of UHF RFID reader digital baseband
~~₹12,000.00~~ ₹6,000.00
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Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
~~₹10,000.00~~ ₹7,000.00
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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
~~₹16,000.00~~ ₹12,000.00
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Concept Design and Implementation of Reconfigurable CORDIC
~~₹15,000.00~~ ₹10,000.00
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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A Floating-Point Fused Dot-Product Unit

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

Area Delay Power Efficient Carry Select Adder

ASIC design of UHF RFID reader digital baseband

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Concept Design and Implementation of Reconfigurable CORDIC