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NXFEE – Area Efficient

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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

₹6,000.00
Sale
Placeholder
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A 65-nm CMOS Constant Current Source With Reduced PVT Variation

₹6,000.00
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Vedic Sutras
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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

₹7,000.00
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BCH Codes
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A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

₹15,000.00
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AES
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A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

₹15,000.00
Sale
Placeholder
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A Floating-Point Fused Dot-Product Unit

₹10,000.00
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Multiply-Accumulate Unit
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A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

₹10,000.00
Sale
Compression
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A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

₹20,000.00
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A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

₹7,000.00
Sale
GDI
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A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

₹9,000.00
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Ternary
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A Review on Fundamentals of Ternary Reversible Logic Circuits

₹10,000.00
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A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

₹7,000.00
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Booth Multiplier
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A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

₹10,000.00
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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

₹7,000.00
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Wallace_Tree
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An Efficient Design for Reversible Wallace Unsigned Multiplier

₹8,000.00
Sale
Floating_Point_Multiplier
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An Efficient Implementation of Floating Point Multiplier

₹14,000.00
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An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

₹10,000.00
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Binary Tree Adder
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Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

₹10,000.00
Sale
Carry Select Adder
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Area Delay Power Efficient Carry Select Adder

₹7,000.00
Sale
Latches
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Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

₹10,000.00
Sale
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ASIC design of UHF RFID reader digital baseband

₹6,000.00
Sale
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Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

₹7,000.00
Sale
Combating Data Leakage Trojans
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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

₹12,000.00
Sale
FIR VEDIC
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Comparative study of 16-order FIR filter design using different multiplication techniques

₹12,000.00
Sale
Compressor
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Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

₹10,000.00
Sale
Implementation of Reconfigurable CORDIC
Implementation of Reconfigurable CORDIC
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Concept Design and Implementation of Reconfigurable CORDIC

₹10,000.00
Sale
Wallace_Tree
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Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs

₹16,000.00
Sale
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Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

₹6,000.00
Sale
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Design of Testable Reversible Sequential Circuits

₹4,000.00
Sale
Image Multiplication
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Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

₹14,000.00
Sale
fixed-width adder-tree
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Efficient Design for Fixed-Width Adder-Tree

₹12,000.00
Sale
ER TCAM
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ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

₹10,000.00
Sale
TCAM Emulated SRAM
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Error Detection and Correction in SRAM Emulated TCAMs

₹15,000.00
Sale
Multiply_accumulate
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Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

₹12,000.00
Sale
TRNG
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FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

₹12,000.00
Sale
Encoder Architecture for Long Polar Code
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FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

₹9,000.00
Sale
FM0Manchester Encoding Using SOLS Technique for DSRC
FM0Manchester Encoding Using SOLS Technique for DSRC
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Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

₹9,000.00
Sale
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Graph-Based Transistor Network Generation Method for Supergate Design

₹4,000.00
Sale
Placeholder
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High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

₹7,000.00
Sale
TSPC D Flip-Flop
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High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

₹4,000.00
Sale
MDCLCG
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High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

₹12,000.00
Sale
Hybird Logic Full Adder
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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

₹12,000.00
Sale
Hybrid full adder
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Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology

₹6,000.00
Sale
Placeholder
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Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

₹12,000.00
Sale
Placeholder
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Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

₹9,000.00
Sale
Traffic Light Controller
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Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA

₹6,000.00
Sale
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Low Power Divider Using Vedic Mathematics

₹7,000.00
Sale
Variation Tolerant Nonvolatile Lookup Table Design
Variation Tolerant Nonvolatile Lookup Table Design
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Low Power Variation Tolerant Nonvolatile Lookup Table Design

₹7,500.00
Sale
CRC_Implementation
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Low-Cost and Programmable CRC Implementation Based on FPGA

₹10,000.00
Sale
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Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

₹7,000.00

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