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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic
A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors
Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology
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