+91 9789443203

Area Efficient

Showing all 52 results

Sale!
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
~~₹7,000.00~~ ₹6,000.00
Add to cart
Sale!
A 65-nm CMOS Constant Current Source With Reduced PVT Variation
~~₹12,000.00~~ ₹6,000.00
Add to cart
Sale!
A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹35,000.00~~ ₹15,000.00
Add to cart
Sale!
A Floating-Point Fused Dot-Product Unit
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace
~~₹35,000.00~~ ₹20,000.00
Add to cart
Sale!
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Area Delay Power Efficient Carry Select Adder
~~₹10,000.00~~ ₹5,000.00
Add to cart
Sale!
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
ASIC design of UHF RFID reader digital baseband
~~₹12,000.00~~ ₹6,000.00
Add to cart
Sale!
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
~~₹16,000.00~~ ₹12,000.00
Add to cart
Sale!
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
~~₹16,000.00~~ ₹10,000.00
Add to cart
Sale!
Concept Design and Implementation of Reconfigurable CORDIC
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Design of Testable Reversible Sequential Circuits
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
Efficient Design for Fixed-Width Adder-Tree
~~₹20,000.00~~ ₹12,000.00
Add to cart
Sale!
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
~~₹18,000.00~~ ₹10,000.00
Add to cart
Sale!
Error Detection and Correction in SRAM Emulated TCAMs
~~₹20,000.00~~ ₹15,000.00
Add to cart
Sale!
Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator
~~₹25,000.00~~ ₹12,000.00
Add to cart
Sale!
FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings
~~₹18,000.00~~ ₹12,000.00
Add to cart
Sale!
FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
Add to cart
Sale!
Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
Graph-Based Transistor Network Generation Method for Supergate Design
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
~~₹12,000.00~~ ₹7,000.00
Add to cart
Sale!
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop
~~₹8,000.00~~ ₹4,000.00
Add to cart
Sale!
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
~~₹16,000.00~~ ₹12,000.00
Add to cart
Sale!
Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Low Power Variation Tolerant Nonvolatile Lookup Table Design
~~₹10,000.00~~ ₹7,500.00
Add to cart
Sale!
Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Obfuscating DSP Circuits via High Level Transformations
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
~~₹10,000.00~~ ₹8,000.00
Add to cart
Sale!
Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Quaternary Logic Lookup Table in Standard CMOS
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
~~₹10,000.00~~ ₹6,000.00
Add to cart
Sale!
Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array
~~₹20,000.00~~ ₹12,000.00
Add to cart
Sale!
Sharing Logic for Built In Generation of Functional Broadside Tests
~~₹10,000.00~~ ₹4,000.00
Add to cart
Sale!
Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders
~~₹18,000.00~~ ₹12,000.00
Add to cart
Sale!
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
~~₹16,000.00~~ ₹8,000.00
Add to cart
Sale!
The Mesochronous Dual-Clock FIFO Buffer
~~₹12,000.00~~ ₹8,000.00
Add to cart
Sale!
Towards Efficient Modular Adders based on Reversible Circuits
~~₹16,000.00~~ ₹10,000.00
Add to cart
Sale!
VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
~~₹12,000.00~~ ₹8,000.00
Add to cart

Cart

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A Floating-Point Fused Dot-Product Unit

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

Area Delay Power Efficient Carry Select Adder

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

ASIC design of UHF RFID reader digital baseband

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

Concept Design and Implementation of Reconfigurable CORDIC

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

Design of Testable Reversible Sequential Circuits

Efficient Design for Fixed-Width Adder-Tree

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Error Detection and Correction in SRAM Emulated TCAMs

Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

Graph-Based Transistor Network Generation Method for Supergate Design

High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA

Low Power Divider Using Vedic Mathematics

Low Power Variation Tolerant Nonvolatile Lookup Table Design

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

Obfuscating DSP Circuits via High Level Transformations

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

Quaternary Logic Lookup Table in Standard CMOS

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

Sharing Logic for Built In Generation of Functional Broadside Tests

Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

The Mesochronous Dual-Clock FIFO Buffer

Towards Efficient Modular Adders based on Reversible Circuits

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding