Proposed Title :
FPGA Implementation of 8-Bit Low Power and High Performance Wallace Tree Multiplier using Reversible Logic Gate
Improvement of this Project:
- To design a 8-Bit Wallace tree multiplier using reversible logic gates, and compare all the reversible logic gates, and given comparisons to 4-bit vs 8-bit parameters.
In any digital gadgets application based arithmetic operations a multiplier will take major role to support several multiplication algorithms, by the way it’s taken more logic size and power consumptions. As per the research of last few decades among various multiplication algorithm, a Wallace tree multiplication will provide effective terms of low logic sizes and more speed of operations. In a recent arithmetic applications based circuit design will have more demand with high speed and low area, in this manner the proposed approach of this work will improve the speed of Wallace tree multiplier using reversible logic method without degrading its area parameter. The proposed multiplication will designed using Verilog HDL, and Synthesis in Xilinx Spartan-6 FPGA, and hence proved all the parameters in terms of number of LUT, slice registers, IOB, delay and power.
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An Efficient Design for Reversible Wallace Unsigned Multiplier
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