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2017

IEEE Transactions on VLSI 2017

Showing all 14 results

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A 6-GS/s 6-bit Time Interleaved SAR-ADC
~~₹12,000.00~~ ₹8,000.00
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A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer
~~₹35,000.00~~ ₹25,000.00
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Design of Power and Area Efficient Approximate Multipliers
~~₹20,000.00~~ ₹12,000.00
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Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers
~~₹16,000.00~~ ₹12,000.00
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Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation
~~₹30,000.00~~ ₹20,000.00
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Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
~~₹12,000.00~~ ₹8,000.00
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High Performance VLSI architecture for M-PSK modems
~~₹16,000.00~~ ₹10,000.00
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Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier
~~₹16,000.00~~ ₹8,000.00
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QPSK Modulator on FPGA
~~₹16,000.00~~ ₹10,000.00
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Resource Efficient SRAM based Ternary Content Addressable Memory
~~₹16,000.00~~ ₹10,000.00
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RF Power Gating A Low Power Technique for Adaptive Radios
~~₹15,000.00~~ ₹10,000.00
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RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing
~~₹16,000.00~~ ₹12,000.00
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Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
~~₹16,000.00~~ ₹8,000.00
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VLSI Implementation of an Edge-Oriented Image Scaling Processor
~~₹20,000.00~~ ₹16,000.00
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A 6-GS/s 6-bit Time Interleaved SAR-ADC

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

Design of Power and Area Efficient Approximate Multipliers

Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers

Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

High Performance VLSI architecture for M-PSK modems

Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier

QPSK Modulator on FPGA

Resource Efficient SRAM based Ternary Content Addressable Memory

RF Power Gating A Low Power Technique for Adaptive Radios

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

VLSI Implementation of an Edge-Oriented Image Scaling Processor