Proposed Title :

Low Power and Energy Efficient Approximate Multiplier Design using Bit Significance Driven Logic Compression

Improvement of this Project:

• To Design a 16 x 16 Approximate Multiplier using bit Significance Driven Logic Compression(SDLC)

Software implementation:

• Modelsim
• Xilinx 14.2

Proposed System:

Approximate computing device in a digital system reduces the design complexity and provide the high efficient solutions in order to increases its performance.  The approximate computation devices reduces the design complexity, power consumption, delay and area in order to increases its performance when compared to exact computing device. The proposed technology of this paper describes the Bit Significance- Driven Logic Compression (SDLC) concept of high efficient approximate multipliers.  The major concept of the proposed multiplier includes lossy compression through logic clustering and remapping the partial products.  Thus, the algorithm of  lossy compression in rows of the partial products  based on their progressive bit significance and the lossy compression is carried out through logic clustering.  Finally, the number of product rows are reduced by remapping the resultant rows of the partial product. Thus, the design complexity of  logic cell count of the multiplier and length of the critical path is drastically reduced when compared to the normal exact multipliers.  The proposed design of the  multiplier are evaluvated in the VHDL and synthesized in the XILINIX 14.2 and compared with area, power and delay.

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Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

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