Proposed Title :
Low Power 10T SRAM-512 Bit Cells with Data Independent Read port leakage array augmentation in 22nm CMOS Technology
Improvement of this Project:
To design Low-Power Near-Threshold three iterations of 10T SRAM with 512 Bit Cells in minimum voltage of 80mV.
To design 512 Bit Cells of 10T SRAM with 22nm CMOS Technology and proved the comparison with existing 10T SRAM Bit Cell with 32nm CMOS.
- TANNER EDA
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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
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