Dual Use of Power Lines for Design for Testability A CMOS Receiver Design

Existing System:

To the best of our knowledge, we are the only group who reported the works on PLC. Our group proposed PLC in ICs to reduce the pin count, size, and hence the cost of a chip initially and later to increase the channel capacity for the multiple parallel scan design. To follow up the proposal, we investigated several relevant topics for PLC in ICs, and reviewed them briefly as follows.

We measured the propagation loss from a core power supply pin to an on-chip node of a PDN of a cold Pentium 4 die (65 nm version). The largest passband was observed ∼2 GHz over a 200-MHz band, and the path loss increases above 40 dB beyond 2.5 GHz. Other measurements were carried out on three different samples of cold 45-nm Core 2 Duo processors and two randomly picked locations on the PDNs. The averaged transfer function shows narrow sporadic passbands, where about 5%∼7% of the input signal passes through the PDN. We observed that there is little correlation between the passbands of the 65 nm Pentium 4 and that for the 45-nm Core 2 Duo processors. We suggested the use of ultra-wideband (UWB) and direct-sequence code division multiple access (DS-CDMA) communication technologies to circumvent the blocking of data signals in low frequencies at packages and PDNs and increase the SNR. Compared with the traditional narrow-band communication systems, UWB signaling has several advantages, such as high data rate, low average power, and simple RF circuitry [31]. Shannon’s theorem states that the channel capacity is given as B×log2(1+SNR),whereBis the bandwidth. As the bandwidth is much larger (on the order of several gigahertz) for UWB than a narrow-band signal, the SNR can be much smaller for UWB to achieve the same data rate. The DS-CDMA technology assigns a codeword to each bit of information called spreading, and orthogonal codewords are assigned to different users or power pins for the PLC in ICs to support multiple channels. The spreading operation represents 1 bit of data as a series of binary pulses spread over a codeword, which increases the pulse repetition frequency. The benefit of spreading is the processing gain, which is 10×log (spreading_ factor) in decibel. For example, the spreading factor for 4-bit codewords is 4, which yields a processing gain of 6 dB, or increases the SNR by 6 dB. We also investigated the modeling of I/O pads and PDNs, and estimated the performance of the proposed PLC systems.

 
Disadvantages:

• Noise immunity is low

Proposed System:

The proposed on-chip PLC receiver receives the data superimposed on power lines, and the data (such as scan test data) are sent from a test instrument. Therefore, the transmitter for the PLC receiver is an external instrument rather than the one on the same chip. The receiver was designed in CMOS 0.18-μm technology with a supply voltage of 1.8 V. It consists of three building blocks, and this section describes the design of each building block.

Block Diagram:

A block diagram of the proposed PLC receiver is shown in Fig. 2. The proposed PLC receiver consists of three blocks, each sharing the same supply voltage (VDD+vdd(t)).The first block is a level shifter, which lowers the dc level of the signal superimposed on the supply voltage. The level shifted signal is processed by the subsequent block, a signal extractor, which amplifies the signal and converts it to a differential signal. The logic restorer, which is a differential Schmitt trigger, recovers logic values from the differential signal.

Level Shifter:

The level shifter shown in Fig. 5 can be treated as a common source amplifier with diode-connected load as, in which the amplifier input is fixed to a bias voltage Vbias. The level shifter propagates the data signal vdd(t) imposed on the supply voltage VDD to the output while lowering the dc voltage level of the signal to 0.5VDD. To propagate the data signal superimposed on the supply voltage to the output, the output should be sensitive to supply voltage variations.

Signal Extractor:

The input signal of the signal extractor is the data signal offset with 0.5 VDD, and the signal extractor amplifies the data signal while removing the dc offset voltage. The signal extractor shown in Fig. 6 is a differential amplifier, in which one input is connected to an RClow-pass filter. The low-pass filter intends to extract the dc value of the signal. The differential amplifier rejects the common-mode signal of the two inputs or the dc value. It also converts a single-ended input into a differential output pair.

Logic Restorer:

The logic restorer translates the data in the form of an analog differential signal into logic values. It is based on the differential Schmitt trigger presented and is shown Fig. 7. A key aspect of the Schmitt trigger is the hysteresis generated through the regenerative feedback circuit, specifically a cross-coupled inverter pair. When a new data signal is applied to the logic restorer, the clock is turned from low to high and turns OFFM5 and M6. It reduces the current supplied to the differential amplifier, which results in a smaller gap between the high and the low threshold voltages. The cross-coupled inverter pair settles to a high or low state, and hence the output of the logic restorer. Then, the clock signal becomes low, andM5 and M6 are turned ON. The gap between the two threshold voltages becomes wider, which increases the immunity to noise and disturbances.

 
 
Advantages:

• Noise immunity is increased

Software implementation:

• DSCH3/Microwind