The larger number of CMOSs has taken large sizes and slow bit streams so speed efficiency is less. To avoid that specificity QCA has introduced in the circuit industry. The QCA is a new technology using quantum dots for digital calculation. This technology decreases power consumption and delay and increases frequency and speed in the transmission of information. QCA has no voltage source; the position of the electrons determines the logical values. QCA is a novel alternative to the CMOS paradigm. Unlike CMOS circuits, the QCA clock is fundamentally different from the data. The clock raises and lowers the barriers between the dots, alternately prohibiting and allowing the electrons to tunnel between dots. Feature size in CMOS has decreased after several decades. However, some limitations still exit. This has caused the rapid development of molecular plans on the nanoscale.
In the existing system the CMOS based implemented memory as parallel read/serial write. We provided a new structure of memory for QCA. Their design attempts incorporate space reduction and application of series memories to decrease delays in reading. This hybrid architecture design is conditional; however, the design network width is 1 bit and it is not possible to save multiple bit data as a data packet. Much attention has been focused on the memory cell core in the QCA devices and the results so far have been encouraging, but more work is needed on the simple architecture of the clock circuitry and peripheral circuit. The objective of this paper is a practical memory cell design for compact memory in QCA.
- Store single bit data
- Parallel read/write operation is more complex
- Circuit design is high
- Used more power.
The area and delay of the QCA-based SRAM cell presented in this paper was compared with the SRAM cell based on CMOS. The results show that the proposed SRAM cell performs with a minimum clock and area. A 16-bit × 32-bit SRAM implemented in QCA with minimum delay in read (R) and write (W) operations uses the least possible area. The 32-bit width makes it possible to save data as a 32-bit data packet in SRAM. This paper had three objectives: 1) minimum delay; 2) improved consumed area and achieving minimum complexity; and 3) achieved read/write (R/W) operation on SRAM frequently and its application as a module to generalize SRAM. Previous studies have simulated circuits using QCA Designer software, but the simulation results of the proposed structure elements are not illustrated. This paper presents the simulation results of the elements used in QCADesigner.
A proposed method consists of building the QCA devices out of single molecules. The expected advantages of such a method include: 1) highly symmetric QCA cell structure; 2) very high switching speeds; 3) extremely high device density; 4) operation at room temperature; and 5) even the possibility of mass-producing devices by means of self-assembly. A number of technical challenges, including choice of molecules, the design of proper interfacing mechanisms, and clocking technology remain to be solved before this method can be implemented.
4-to-16 Decoder :
The 4-to-16 decoder in the first stage uses eight two-input AND gates. The inputs of the AND gates are connected to input wires A, B, C, and D. The 4-to-16 decoder in the second stage uses eight two-input AND gates to enable or disable the output. The 16 outputs are generated by a 4 × 4 two-input AND gate network.
16 to 1 Multiplexer:
The 16-to-1 MUX is composed of 24 three-input majority gates to implement two-input AND and OR gates in the first stage and 12 three-input majority gates to implement the two-input AND and OR gates in the second stage and nine three-input majority gates to implement the two-input AND and OR gates in the third and fourth stages. This is necessary to the design of the 16-bit × 32-bit SRAM.
SRAM continues to be a fundamental and vitally important memory technology. They are fast, robust, and easily manufactured in standard logic processes, and nearly universally found on the same die with microcontrollers and microprocessors. The demand for ever larger and ever faster microprocessors has aggressively driven the scaling of transistor geometries down and the density and speed of the SRAM cells up.
16-bit × 32-bit SRAM:
Here memory cells are located in the 16-bit × 32-bit arrays. As shown in the fig.1 the 4-to-16 decoder addresses the 16 SRAM lanes. This SRAM has four addressing lines that can address up to 16 SRAM lanes. After selecting the desired SRAM lane, 32 bits of data can be written or read in accordance with the R/W line. The read or write operation from one 32-bit SRAM lane is applied in accordance with the path delays and occurs at the same clock. Data from the SRAM lanes are transferred to the output by a 16-to-1 MUX in read mode. The four lines of the addressing decoder are connected to four switch lines of the MUX jointly and the output line of the MUX is selected by the addressing decoder. A 32-bit bus is connected commonly to all SRAM lanes and is used to enter the data into the SRAM lane in write mode.
Proposed 256x32bit SRAM:
The 16-bit × 32-bit SRAM can be considered a module with a constant structure and correct clocking. First, combine eight modules with suitable connections to produce a 256-bit × 32-bit SRAM. This is used to indicate that the 32-bit data bus is connected to the 32-bit data bus of the 16-bit × 32-bit SRAMs. Addressing eight 16-bit × 32-bit SRAMs is performed by the 4-to-16 decoder. Data from the 16-bit × 32-bit SRAMs are transferred to the output by an 16-to-1 MUX in read mode. The three lines of the addressing decoder are connected to three switch lines of the MUX jointly and the output line of the MUX is selected by the addressing decoder.
- serial read/write operation
- multiple bit support
- Low power consumption.