Sale

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

₹7,000.00

Sale

2016, Area Efficient, IEEE, VLSI

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

₹6,000.00

Sale

2019, Low power VLSI Design, VLSI

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

₹10,000.00

Sale

2019, Low power VLSI Design, VLSI

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

₹6,000.00

Sale

2019, Low power VLSI Design, VLSI

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

₹8,000.00

Sale

2020, Low power VLSI Design, VLSI

A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

₹10,000.00

Sale

2017, Low power VLSI Design

A 6-GS/s 6-bit Time Interleaved SAR-ADC

₹8,000.00

Sale

2016, Area Efficient

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

₹6,000.00

Sale

2019, Low power VLSI Design, VLSI

A 7T Security Oriented SRAM Bitcell

₹6,000.00

Sale

2016, Image Processing, VLSI

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

₹20,000.00

Sale

2020, Low power VLSI Design, VLSI

A Compact 0.3 V Class AB Bulk Driven OTA

₹6,000.00

Sale

2015, Area Efficient

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

₹7,000.00

Sale

2016, Image Processing

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

₹20,000.00

Sale

2015, Image Processing

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

₹10,000.00

Sale

2019, Area Efficient, VLSI

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

₹15,000.00

Sale

2020, Area Efficient, VLSI

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

₹15,000.00

Sale

2014, Area Efficient, VLSI

A Floating-Point Fused Dot-Product Unit

₹10,000.00

Sale

2016, Low power VLSI Design

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

₹9,000.00

Sale

Transistor Static Topology Shift Register

2014, Low power VLSI Design

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

₹7,000.00

Sale

2015, Low power VLSI Design

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

₹8,000.00

Sale

2016, Low power VLSI Design, VLSI

A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity

₹10,000.00

Sale

2016, High speed VLSI Design

A High Speed FPGA Implementation of an RSD Based ECC Processor

₹10,000.00

Sale

2020, Area Efficient, VLSI

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

₹10,000.00

Sale

2019, Area Efficient, VLSI

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

₹20,000.00

Sale

2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

₹6,000.00

Sale

2020, High speed VLSI Design, VLSI

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

₹8,000.00

Sale

2019, High speed VLSI Design, VLSI

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

₹15,000.00

Sale

2014, Low power VLSI Design

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

₹10,000.00

Sale

2018, Low power VLSI Design, VLSI

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network

₹6,000.00

Sale

2015, Low power VLSI Design

A Low Power Architecture for the Design of a One Dimensional Median Filter

₹8,000.00

Sale

2015, Area Efficient

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

₹7,000.00

Sale

2016, Low power VLSI Design

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

₹6,000.00

Sale

2016, High speed VLSI Design

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

₹25,000.00

Sale

2019, Low power VLSI Design, VLSI

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

₹6,000.00

Sale

2016, Image Processing

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

₹6,000.00

Sale

2019, Area Efficient, VLSI

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

₹9,000.00

Sale

2015, High speed VLSI Design

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

₹8,000.00

Sale

2017, Image Processing, VLSI

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

₹25,000.00

Sale

2020, Area Efficient, VLSI

A Review on Fundamentals of Ternary Reversible Logic Circuits

₹10,000.00

Sale

2016, Area Efficient, IEEE, VLSI

A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

₹7,000.00

Sale

2020, Low power VLSI Design, VLSI

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

₹6,000.00

Sale

2019, Low power VLSI Design, VLSI

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

₹6,000.00

Sale

2015, Low power VLSI Design

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

₹6,000.00

Sale

2021, Low power VLSI Design, VLSI

A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

₹8,000.00

Sale

2019, Area Efficient, VLSI

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

₹10,000.00

Sale

2015, Image Processing

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

₹7,000.00

Sale

2020, NOC VLSI Design, VLSI

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

₹15,000.00

Sale

2015, Low power VLSI Design

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

₹7,000.00

Sale

2019, High speed VLSI Design, VLSI

An Analog LO Harmonic Suppression Technique for SDR Receivers

₹12,000.00

Sale

2015, Area Efficient

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

₹7,000.00

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VLSI RESEARCH TITLES

2021 TITLES

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2019 TITLES

2018 TITLES

DOWNLOAD VLSI SOFTWARES

MENTOR MODELSIM V15.1.0

MENTOR QUESTASIM V10.4c

XILINX V14.5

Gvim

QUARTUS V15.0

Tanner V16

Tanner V13

MATLAB R2018a_64bit

MATLAB R2014a

Teamviewer

Any desk

DOMAIN ZONE

Low Power VLSI Design