sale OFFER 63%

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

sale OFFER 63%

2016, Area Efficient, IEEE, VLSI

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

sale OFFER 44%

2019, Low power VLSI Design, VLSI

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

sale OFFER 20%

2019, Low power VLSI Design, VLSI

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

sale OFFER 44%

2019, Low power VLSI Design, VLSI

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

sale OFFER 33%

2020, Low power VLSI Design, VLSI

A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

sale OFFER 50%

2017, Low power VLSI Design

A 6-GS/s 6-bit Time Interleaved SAR-ADC

sale OFFER 50%

2016, Area Efficient

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

sale OFFER 50%

2019, Low power VLSI Design, VLSI

A 7T Security Oriented SRAM Bitcell

sale OFFER 33%

2016, Image Processing, VLSI

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

sale OFFER 50%

2020, Low power VLSI Design, VLSI

A Compact 0.3 V Class AB Bulk Driven OTA

sale OFFER 44%

2015, Area Efficient

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

sale OFFER 71%

2016, Image Processing

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

sale OFFER 57%

2022, Area Efficient, VLSI

A Configurable Floating Point Multiple Precision Processing Element for HPC and AI Converged Computing

sale OFFER 36%

2015, Image Processing

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

sale OFFER 66%

2019, Area Efficient, VLSI

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

sale OFFER 50%

2020, Area Efficient, VLSI

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

sale OFFER 38%

Accessories, VLSI, VLSI 2025

A Design of lightweight true random number generator based on Galois LFSR with dynamic feedback path

sale OFFER 40%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

A Dual-Mode ECG Segment Export Tool with RGB and Grayscale Hex Encoding in MATLAB

sale OFFER 44%

2014, Area Efficient, VLSI

A Floating-Point Fused Dot-Product Unit

sale OFFER 63%

2016, Low power VLSI Design

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

sale OFFER 33%

2014, Low power VLSI Design

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

sale OFFER 29%

2015, Low power VLSI Design

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

sale OFFER 50%

2016, Low power VLSI Design, VLSI

A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity

sale OFFER 50%

Area Efficient, VLSI, VLSI 2024

A High Speed CRC-32 Implementation on FPGA

sale OFFER 60%

2016, High speed VLSI Design

A High Speed FPGA Implementation of an RSD Based ECC Processor

sale OFFER 44%

2020, Area Efficient, VLSI

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

sale OFFER 60%

2022, High speed VLSI Design, VLSI

A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers

sale OFFER 54%

2019, Area Efficient, VLSI

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

sale OFFER 50%

2022, Area Efficient, VLSI

A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder

sale OFFER 50%

2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

sale OFFER 33%

2020, High speed VLSI Design, VLSI

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

sale OFFER 40%

Area Efficient, VLSI, VLSI 2024

A Hybrid TRNG-PRNG Architecture for High-Performance and Resource-Efficient Random Number Generation on FPGA

sale OFFER 50%

Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

A Lightweight True Random Number Generator for Root of Trust Applications

sale OFFER 60%

2019, High speed VLSI Design, VLSI

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

sale OFFER 63%

2021, Image Processing, VLSI

A Low Cost and High Throughtput FPGA Implementation of the Retinex Algorithm for Real Time Video Enhancement

sale OFFER 40%

Image Processing, VLSI, VLSI 2024

A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm

sale OFFER 50%

2014, Low power VLSI Design

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

sale OFFER 20%

2018, Low power VLSI Design, VLSI

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network

sale OFFER 38%

2015, Area Efficient

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

sale OFFER 76%

2016, Low power VLSI Design

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

sale OFFER 67%

2016, High speed VLSI Design

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

sale OFFER 43%

2019, Low power VLSI Design, VLSI

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

sale OFFER 60%

2016, Image Processing

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

sale OFFER 40%

2019, Area Efficient, VLSI

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

sale OFFER 50%

Area Efficient, VLSI, VLSI 2024

A Novel Design of High Speed Multiplier Using Hybrid Adder Technique

sale OFFER 50%

2022, Area Efficient, VLSI

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

sale OFFER 44%

2015, High speed VLSI Design

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

sale OFFER 50%

2021, High speed VLSI Design, VLSI

A Pipelined Reduced Complexity Two Stages Parallel LMS Structure for Adaptive Beam forming

sale OFFER 56%

2017, Image Processing, VLSI

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

sale OFFER 40%

2022, Low power VLSI Design, VLSI

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

sale OFFER 20%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

A Reversible Processor Architecture and Its Reversible Logic Design

sale OFFER 29%

2020, Area Efficient, VLSI

A Review on Fundamentals of Ternary Reversible Logic Circuits

sale OFFER 40%

2020, Low power VLSI Design, VLSI

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

sale OFFER 33%

2019, Low power VLSI Design, VLSI

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

sale OFFER 63%

2015, Low power VLSI Design

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

sale OFFER 33%

2021, Low power VLSI Design, VLSI

A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

sale OFFER 60%

2019, Area Efficient, VLSI

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

sale OFFER 40%

2022, Area Efficient, VLSI

A Unified Approach for Realization of IIR Filters in Delta Domain

sale OFFER 60%

2015, Image Processing

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

sale OFFER 40%

High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

A VLSI-Based Hybrid ECG Compression Scheme for Wearable Sensor Node

sale OFFER 40%

2020, NOC VLSI Design, VLSI

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

sale OFFER 50%

2022, Area Efficient, VLSI

Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation

sale OFFER 50%

2015, Low power VLSI Design

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

sale OFFER 50%

2022, Area Efficient, VLSI

Algorithm Level Error Detection in Low Voltage Systolic Array

sale OFFER 60%

2019, High speed VLSI Design, VLSI

An Analog LO Harmonic Suppression Technique for SDR Receivers

sale OFFER 60%

2021, Area Efficient, VLSI

An Efficient and High Speed Overlap Free Karatsuba Based Finite Field Multiplier for FPGA Implementation

sale OFFER 44%

2015, Area Efficient

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

sale OFFER 38%

2018, Area Efficient, VLSI

An Efficient Design for Reversible Wallace Unsigned Multiplier

sale OFFER 53%

Image Processing, VLSI, VLSI 2023, VLSI_2023

An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys

sale OFFER 50%

2014, Area Efficient, VLSI

An Efficient Implementation of Floating Point Multiplier

sale OFFER 60%

2018, High speed VLSI Design, VLSI

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

sale OFFER 50%

2014, High speed VLSI Design

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

sale OFFER 20%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

An Innovative Area Efficient Pixel Shuffling Method for Image Encryption Algorithm

sale OFFER 33%

2014, Area Efficient, VLSI

An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA

sale OFFER 68%

Image Processing, VLSI, VLSI 2023, VLSI_2023

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

sale OFFER 63%

2020, Area Efficient, VLSI

Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors

sale OFFER 50%

Accessories, Area Efficient, VLSI, VLSI 2024

Approximate Multiplier Design with LFSR-Based Stochastic Sequence Generators for Edge AI

sale OFFER 50%

2021, High speed VLSI Design, VLSI

Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing

sale OFFER 62%

2018, High speed VLSI Design

Approximate Sum-of-Products Design Based on Distributed Arithmetic

sale OFFER 50%

2022, Image Processing, VLSI

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation

sale OFFER 29%

2020, Area Efficient, VLSI

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

sale OFFER 33%

2014, Area Efficient

Area Delay Power Efficient Carry Select Adder

sale OFFER 60%

2019, Area Efficient, VLSI

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

sale OFFER 43%

2019, Image Processing, VLSI

Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

sale OFFER 50%

2015, Area Efficient

ASIC design of UHF RFID reader digital baseband

sale OFFER 50%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

AxPPA: Approximate Parallel Prefix Adders

sale OFFER 60%

2015, Image Processing

Block Interleaver Design for High Data Rate Wireless Networks

sale OFFER 50%

2015, Area Efficient

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

sale OFFER 44%

2019, Low power VLSI Design, VLSI

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

sale OFFER 40%

2019, Low power VLSI Design, VLSI

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

sale OFFER 50%

2019, Low power VLSI Design, VLSI

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

sale OFFER 67%

2018, Area Efficient

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

sale OFFER 50%

2017, Area Efficient, VLSI

Comparative study of 16-order FIR filter design using different multiplication techniques

sale OFFER 38%

2020, Area Efficient, VLSI

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

sale OFFER 40%

2016, Area Efficient

Concept Design and Implementation of Reconfigurable CORDIC

sale OFFER 43%

2019, Image Processing, VLSI

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

sale OFFER 29%

2022, Area Efficient, VLSI

Design and Analysis of a Majority Logic Based Imprecise 6-2 Compressor for Approximate Multipliers

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