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A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC
A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform
A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder
A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
A Low Cost Low Power All Digital Spread Spectrum Clock Generator
A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic
A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer
A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
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