Proposed Title :
FPGA Implementation of Image Encryption and Decryption Algorithm which using Image Line Buffer based Pixel Shuffling method
Improvement of this project :
Introduced a Image Line Buffer 5×5 with Image Encryption Algorithm
Pixel Shuffling done with Column and Row based approach with using Pseudo Random Interleave method and Bit Shifting method.
Data Encryption and Decryption standard done with 64-bit size.
Both Encryption and Decryption was done and proved the original Image with PSNR and SSIM.
Size of Image resolution done with 130 x 130.
Image encryption and decryption algorithms using a line buffer-based pixel shuffling method can enhance the security of image data. The idea is to shuffle pixels in a controlled manner to introduce complexity and make it difficult for unauthorized users to understand the original content without the decryption key. Below is a simple outline of an algorithm that uses a line buffer-based pixel shuffling method for image encryption and decryption. The image line buffer based pixel shuffling technique presented in this study is an alternative to the classic method, which takes up more logic space in VLSI implementations. This proposed method splits and reconstructs the source image using a 5×5 image line buffer. With the use of interleave techniques, this pixel shuffling approach handled row and column sequence using this 5×5 image line buffer. This work introduces a novel implementation of the Data Encryption and Decryption Standard algorithm using Image Encryption that prioritizes security, high throughput, and space efficiency. The proposed solution involves the creation of a system that utilizes a block size of 64 bits and a key length that is also 64 bits. These applications also facilitate the comparison of Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) values. The internal architecture of the system is implemented using Verilog Hardware Description Language (HDL). Additionally, the simulation is conducted using Modelsim. Furthermore, the system’s performance parameters, including area, delay, and power consumption, are compared with those of the Xilinx Vertex-5 Field Programmable Gate Array (FPGA).
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An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys
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