A closed-circuit television (CCTV) is used for urban security and environmental monitoring. In the set-up of smart cities, home video surveillance system provides the necessary visual information to improve situational awareness, to enhance security, to deter possible theft, and to provide remote monitoring. But the output image of CCTV may have low resolution (LR) or loss of information because of the condition of camera setup and lighting. To solve the problem, embedded video super-resolution approach can be implemented and connected directly to CCTV. This enables real time processing with faster and more optimized algorithm. In this paper, we propose Super-Resolution (SR) algorithm for real time hardware implementation. The proposed algorithm is based on the bi-cubic interpolation. The organization of this paper is as follows: the single image SR is presented in section II, the experimental set-up and the simulations are discussed in Section III, and in Section IV, the results and analysis is presented followed by the conclusion.
Single Image Super Resolution:
Single image SR is the method to increase resolution from only single image LR input. The reconstruction step is simple and can achieve faster processing algorithm than multiple image SR. In the followings, we explain reference algorithm, bi-cubic interpolation and sparse representation.
Bi-Cubic Interpolation based Method:
Bi-cubic interpolation was firstly proposed in with several variations to increase the performance. The general weakness of this approach is the blur on the edge and corner of the image as the result of integrating sharpening and smoothing process. Moreover, research applied back projection kernel p to increase the image resolution by using LR error, as shown in (1), in which LR image is Y, HR image is X and with iteration t. However, it still has chessboard and ringing effect on the reconstructed image.
- Very Low PSNR, SSIM in Bi-Cubic Interpolation
- Area, Delay and Power will take more
In the recent years of image processing application of super resolution technique will increases a resolution day by day in lot of application, here this paper presents a Traffic controlling and monitoring through CCTV modules. In this CCTV based super resolution of Bi-cubic interpolation will not get the clarity in vehicle motion pictures at moving time. So this paper proposed this work with Interpolation such as Bi-Cubic method based Vertical and Horizontal Interpolation at taken the image of low resolution to interpolate to High resolution (1600×1600) pixel size.
As previously described, we assume LR image is a part of HR image. The proposed method needs to keep information of the LR image to reconstruct HR image for real time hardware processing. We propose algorithm based on Bi-cubic Interpolation to minimize the processing time but at the same time, to improve the reconstructed image quality as well. Our proposed method named overlapping bi-cubic interpolation updates the different new LR image with the original LR image to HR image.
The demand of the digital image processing technology from the social different domain growing at present day by day, some complex and effective algorithms of imagery processing related domain have been proposed. Usually, there are mainly two methods  to raise the imagery processing speed. First, carry on the optimization to the imagery processing algorithm. Simplifies the algorithm to raise the running speed of the algorithm, but the precision is very difficult to guarantee. Second, change the way to realize the algorithm. Considered the convenience and the cost, the imagery processing algorithm is realized generally with the form of software programming. The processing speed meets the timely need difficulty, because of standard serial processing method. The imagery processing speed can be raised, and the high speed  requirements can be met by the way of the software and hardware design for the algorithm which is simple structure, large quantity data and parallel character. FPGA, which is programmable logical component, not only has the characteristic of big scale, high integration rate and high reliable as ASIC, but also maintained the characteristic of short design cycle, lowly development invested and high flexibility as PLD. The central processors (CPU), the multiplier, the digital processor (DSP) have been integrated in new generation FPGA. DSP are unable to compare with the hardware parallel processing and the stream line operation of FPGA. Therefore the application of FPGA in the digital image processing domain is quite ideal choice.
Bi-Cubic computation module:
We know that calculating the value of an interpolation picture element need carry on the level and the vertical convolution operation of 16 spots picture element 4×4 matrices according to the introduction of the Bi-cubic interpolation enlargement algorithm. The value of a temporary reference spot can be obtained by convolution operation from 4 picture element with the respective weight value in the horizontal direction. The value of an interpolation picture element can be obtained by the second convolution operation from the values of direction four temporary reference spots with the respective weight value again in the vertical direction. The independent D trigger, the multiplier and the accumulator will be used in the traditional design in such computation, in, will use realizes. The arithmetic circuit will be numerous and diverse. The weight h can be calculated and obtained by search table way of the Bi-cubic interpolation enlargement algorithm which is improved as 2.2 in this paper. Realize the Bi-cubic interpolation enlargement algorithm by ALTMULT_ADD, LPM_MULT, PARALLEL_ADD which are provided by LPM of Xilinx Vertex 5 FPGA.
The ALTMULT_ADD,LPM Multiplier, can set the input port number, the bit width of data and the clock control by the user needs. The module can carry out the multi-port multiplication respectively and add the calculated results of various quarters as the output.
The LPM_MULT, LPM multiplier, can greatly improve the efficiency and performance of the multiplication. After setting parameters simply, it can complete the tow-way multiplication between the data with signed and unsigned. It also can complete the multiplication between the signal square summation input and the constant. The witch of the input can be automatically calculated. The difficulty of the design becomes simple.
The PARALLEL_ADD,LPM parallel adder, can be defined the number of input ports for the multiplication and the witch of data according to the user needs. The module can add separate data parallel and automatically generate the output data bit witch to meet the requirements. The user also can improve the performance by adding the displacement function of registers and line control. The convolution operation in four horizontal direction of the pixel matrix is completed by four multipliers in this article. Then the four calculation results multiply with their respective weight in the corresponding LPM_MULT. Finally, the convolution operation in the vertical direction is completed through the parallel adder. The interpolated points can be as output. The whole process of the calculation is shown in Figure 1. Shown in Figure1, the box stands for the ALTMULT_ADD in the fourth row of the four row convolution operation on the horizontal direction. Its input port dataa_0[7..0] connects to output port of the data cache module taps0x.It receives all the values of the fourth line(P9ǃP10ǃP11 and P12) of the 4 4 × pixel matrix and has a displacement.
- Increases the PSNR, SSIM Level in Bicuibc Interpolation
- Reduced the Area, Delay and Power.