Proposed Title :
FPGA Implementation of Fully Pipelined Super Resolution Color Demosaicking for Real Time Video Application
Improvement of this project :
To design the Fully Pipelined Super Resolution Color Demosaicking technique using Bi-Cubic interpolation to increases the PSNR and SSIM.
To design the SR-Demosaicking Hardware machine using Carry Skip adder and proved the performance with conventional method.
Successfully execute this work in Xilinx FPGA using VHDL and compared all the parameters in terms of area, delay and power.
Software Implementation:
- Questa Sim
- Xilinx – Vivado
Proposed System:
In addition to the resolution of the images that are acquired, there are other factors that could impact whether or not the whole color of a scene can be obtained. Since digital cameras receive an incomplete set of color image, the mosaic picture format is the one that is recommended for use with these devices. In this research, a super resolution demosaicking (SRD) technique is developed with the goal of reconstructing an enhanced-resolution full-color image from the samples that have been seen in a way that is both resilient and does not need a training procedure. The acquisition model operates under the assumption that the observations are degraded, employing blur and noise that is previously known, in the method of reconstruction, unknown registration parameters and the demosaicking are concurrently estimated via a process of iterative estimation. High performance pictures are discovered by the conduct of qualitative and quantitative tests on synthetic observations. To design the Fully Pipelined Super Resolution Color Demosaicking technique using Bi-Cubic interpolation to increases the PSNR and SSIM. This proposed work to design the SR-Demosaicking Hardware machine using Carry Skip adder and proved the performance with conventional method, and execute this work in Xilinx FPGA using VHDL and compared all the parameters in terms of area, delay and power.
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Image Demosaicking using Super Resolution Techniques
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