Proposed Title :

FPGA Implementation of Floating Point Discrete Wavelet Transform using 32-Tap Direct Form FIR Filter

Improvement of this Project:

• To design the FIR filter at 32-Tap filter order to increases the efficiency of discrete wavelet transform.

• To resolve the transpose form extra padding 0 addition in the FIR filter and done the FIR filter design using direct form.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

In a recent technology, image compression is a most priority one in all digital gadgets, which using image and video transmission and receptions, it’s reducing the data storage and increasing the data delivery time. Thus, this work present a image compression method using discrete wavelet transform with support of floating point addition and multiplication method. This floating point representation offer more higher precision and better accuracy compared to scaled integer values. Proposed work of this paper presents to increases the efficiency of the DWT using 32-TAP FIR filter instead of existing 4-TAP FIR filter, and resolve the transpose form extra padding zero addition in the FIR filter and done the FIR filter design using direct form. Finally this work design using verilog HDL and synthesized Xilinx Vertex 5 FPGA and compared all the parameters in terms of area, delay and power.

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Floating-point discrete wavelet transform-based image compression on FPGA