Proposed Title :
A 45nm and 65nm CMOS Implementation of Three Stage Comparator Analysis to reduced Low Kickback Noise
Improvement of this Project:
To design a Miyahara two stage comparator, Three stage comparator and proposed modified version of three stage comparator in 65 nm and 45 nm CMOS technology instead of 130 nm CMOS Technology.
- Tanner EDA
This article describes a three stage comparator and its improved version, which improves speed and lowers kickback noise. The three stage comparator in this study has an extra amplification step compared to standard two stage comparators, which enhances the voltage gain and speed. Unlike the standard two stage architecture, which employs PMOS input pairs in the regeneration stage, the three stage comparator allows NMOS input pairs to be used in both the regeneration and amplification stages, improving efficiency even more. In addition, in the amplification step of the proposed modified three stage comparator, a CMOS input pair is used by cancelling out the NMOS kickback through the PMOS kickback, the kickback noise is considerably reduced. In the regeneration step, it also adds an extra signal line, which helps to boost the speed even more. Both the traditional two stage and the new three stage comparator are built the same 65nm and 45nm CMOS Technology for simple comparisons. The improved version of the three stage comparator improves speed and reduces kickback noise by 10 times, according to the results. This enhancement come at no expense in terms of input referred offset or noise. Finally this work was developed in Tanner EDA and compared all the parameters in terms of area, delay and power.
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A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback
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