Proposed Title :
FPGA Implementation of Gaussian Smoothing Colour Filter using Image Line Buffer
Improvement of this Project:
To implement Gaussian Smoothing Filter with using Image line Buffer to split and reconstruct 3×3 image convolution at the 720×576 image resolution instead of 640×480.
Also implemented with Colour images Red, Green and Blue.
- Xilinx 14.2
This work develops and present a unique and extremely efficient hardware architecture for a Image line buffer based 3×3 filter instead of bit serial implementation of a 3×3 filter on FPGA. The technique is demonstrated using a Gaussian blur spatial filter, but it may be applied to other filter that have comparable properties. The proposed single instruction multiple data architecture maintains a consistent running time regardless of the image resolution, while its reducing architecture to number of addition and accumulation. Here, this proposed work implemented with four steps of addition accumulations such as (West, North, South and East) and designed 720×576 image resolution instead of 640×480 image resolution. The performance of Multiple instruction multiple data is accomplished at a fraction of the cost. As a result, the hardware efficiency is optimized. The overall time required to apply the desired filter to an image is exclusively determined by the working clock frequency. Finally, this work was developed in Verilog HDL and synthesized in Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.
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Constant Time Hardware Architecture for a Gaussian Smoothing Filter
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