Proposed Title :
FPGA Implementation of XOR – MUX full adder
using Multiplier Free Galois Field Fourier Transform Implementation
Improvement of this Project:
To design a Galosis Field Fourier Transform using XOR MUX full adder design instead of conventional full adder design, and developed with Serial In Parallel Out, Parallel In Serial Out, and Optimized Serial In and Parallel Out architecture and compare all the parameters in terms of Area, delay and Power.
- Xilinx 14.2
The symbols from a vector representation to a power representation by unique technique to performing the Galois Field Fourier Transform is given that fully removes the requirement for any finite field multipliers. On recent FPGA implementation with a considerable quality of on-chip distributed embedded memory. The proposed approach of this work to design a Galosis Field Fourier Transform with minimum number of logic gates to reduce the complexity in FPGA implementation and increases the multiplier speed for that the proposed approach introduced a XOR MUX full adder design instead of conventional full adder design, and developed this approach with Serial In Parallel Out, Parallel In Serial Out, and Optimized Serial In and Parallel Out architecture and compare all the parameters in terms of Area, delay and Power.
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Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA
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