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A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

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Source Code : VHDL
Abstract:
This paper presents a modern low- complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability. We have to use the two type of error correction technique for 128bit; first one is single bit error correction by using the hamming code. This hamming code is detects and then correct the single bit error correction. Another one is multiple bits error correction by using BCH (Bose–Choudhury– Hocquenghem). This one corrects the multiple bits error. Finally these are implemented and get the simulated result is compared to the previous architecture. The code are simulated and power, area, cost are taken using Xilinx 14.2 software.
List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison
3. Architecture Diagram
4. Algorithm with Flow chart
5. Report for Phase1 and Phase2
6. Proposed abstract document
7. Reference materials
8. Literature survey with Reference Document
9. Online Support ( Team viewer/ Ammy Admin)
Proposed System:
In proposed system to reduce the error in the output of the functional block. In this to use two mean structures that are Cross Code Parity Predictor and Correction Block. We are use the 128bit input data for this proposed system.
 
These codes are important for two reasons:

  1. They admit a relatively easy decoding scheme;
  2. The class of BCH codes is quite extensive

Let f(x) be an irreducible polynomial of degree n over a field IF and let α be a root of f(x). Then by replacing x in IF[x] mod (f(x)) by α, we obtain the field represented as,                                                                                                            Advantages:

  • Error correction is mode for multiple bits
  • Accuracy is high
  • Coverage area is reduced

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