Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

Existing System:
Modified Booth (MB) encoding tackles the aforementioned limitations and reduces to half the number of partial products resulting to reduced area, critical delay and power consumption. However, a dedicated encoding circuit is required and the partial products generation is more complex.
Disadvantage : 

• Delay is high

Proposed System :
In the proposed system reduce the delay and efficient architecture of the pre-encoder multiplier design.In this section, we present the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique. As in MB form, the number of partial products is reduced to half. When encoding the 2’s complement number B, digits b^NR_j⁻ take one of four values: {−2, −1, 0, +1} or b^NR+ _j ∈ {−1, 0, +1, +2} at the NR4SD− or NR4SD+ algorithm, respectively. Only four different values are used and not five as in MB algorithm, which leads to 0 ≤ j ≤ k − 2. As we need to cover the dynamic range of the 2’s complement form, the most significant digit is MB encoded (i.e., b^MB _k−1 ∈ {−2,−1, 0, +1, +2}).
Advantages :

• Delay is low

Software implementation :

• Model sim
• Xilinx 14.2

Literature survey:

• “High-Speed Booth Encoded Parallel Multiplier Design,” This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.

• “A 16-Band Reconfigurable Hearing Aid using Variable Bandwidth Filters,” A highly re-configurable non-uniform digital FIR filter bank structure is proposed for the hearing aid application. The non-uniform spaced sub bands are realized with variable bandwidth filters (VBF). Each VBF is implemented as a combination of two arbitrary sample rate converters and a fixed bandwidth FIR low pass filter and the same can be implemented in application specific integrated circuit (ASIC) for the general purpose application to correct any hearing loss pattern. The bandwidths of the channels to suit the optimized audiogram fitting, corresponding frequency shift and bandwidth ratio with respect to the fixed filter are the re-configurable parameters which need modification to achieve the re-configurability. The results of the tests on various hearing loss patterns show that with optimal selection of the band edges of each band, the proposed method achieves better matching between audiograms and the magnitude responses of the filter bank. The cost of hearing aid can be reduced. It can also be made reconfigurable with minimum modification in the programmable part.

• “ROM-based logic (RBL) Design: a low-power 16 bit multiplier,” We present a ROM-based 16 times 16 multiplier for low-power applications. The design uses sixteen 4 times 4 ROM-based multiplier blocks followed by carry-save adders and a final carry-select adder (all ROM-based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement results in 0.18 mum CMOS process show a 40% reduction in power over the conventional carry-save array multiplier when operated at its maximum frequency. The ROM-based design also provides 44% less delay than the array multiplier with a minimal increase (7.7%) in power. This demonstrates the low-power operation of the ROM-based multiplier also at higher frequencies.

• “Design of FIR Filter by using Sharing Multiplier with Low Delay,” The main idea is to represent the multiplication in FIR filtering operation as a combination of add and shift operations over the common computation results. The common computations are identified by decomposing the coefficients of FIR filters. These computations are performed only once and shared Multiplier approach that achieves high performance in FIR filtering with less overhead. The performance of the proposed implementation is compared with implementations based on multipliers like Wallace Tree Multiplier (WTM) (Delay 13.2ns & Area 146 LUTS) & Booth Multiplier(Delay 26.642ns & Area 180 LUTS) .We show that sharing multiplier scheme improves the parameters like Delay & Area with respect to the FIR filter implementations based on the Booth Multiplier & Wallace tree Multiplier.