- Here, the existing system design will be implemented on the sliding function, on 3×1, and 7×1, and here proposed system we are implemented to increases the size of sliding function of 8×1, and also increases the number of iterations to calculate the matrix vector multiplication. So it will support of all high speed data transmission of digital signal processing, image processing, with software define radio technologies.
- Here, is the design for Self based, matrix vector multiplication, this design architecture we are proposed to increases the K, and N size, based on the selector function of 8×1.
- Increases the processing speed
- Reduced the delay
- Reduced the power consumption
- Xilinx 14.2